Datasheet

220
32072H–AVR32–10/2012
AT32UC3A3
16.3 Block Diagram
Figure 16-1. SDRAM Controller Block Diagram
16.4 I/O Lines Description
Memory
Controller
Power
Manager
CLK_SDRAMC
SDRAMC
Chip Select
SDRAMC
Interrupt
SDRAMC
User Interface
Peripheral Bus
I/O
Controller
SDCS
SDCK
SDCKE
BA[1:0]
RAS
CAS
SDWE
DQM[0]
SDRAMC_A[9:0]
D[15:0]
EBI
MUX Logic
DATA[15:0]
SDCK
SDCKE
NCS[1]
RAS
CAS
ADDR[17:16]
SDWE
ADDR[0]
DQM[1]
NWE1
ADDR[11:2]
SDRAMC_A[10]
SDA10
SDRAMC_A[12:11]
ADDR[13:14]
Table 16-1. I/O Lines Description
Name Description Type Active Level
SDCK SDRAM Clock Output
SDCKE SDRAM Clock Enable Output High
SDCS SDRAM Chip Select Output Low
BA[1:0] Bank Select Signals Output
RAS Row Signal Output Low
CAS Column Signal Output Low
SDWE SDRAM Write Enable Output Low