Datasheet

219
32072H–AVR32–10/2012
AT32UC3A3
16. SDRAM Controller (SDRAMC)
Rev: 2.2.0.4
16.1 Features
• 128-Mbytes address space
• Numerous configurations supported
– 2K, 4K, 8K row address memory parts
– SDRAM with two or four internal banks
– SDRAM with 16-bit data path
• Programming facilities
– Word, halfword, byte access
– Automatic page break when memory boundary has been reached
– Multibank ping-pong access
– Timing parameters specified by software
– Automatic refresh operation, refresh rate is programmable
– Automatic update of DS, TCR and PASR parameters (mobile SDRAM devices)
• Energy-saving capabilities
– Self-refresh, power-down, and deep power-down modes supported
– Supports mobile SDRAM devices
• Error detection
– Refresh error interrupt
• SDRAM power-up initialization by software
• CAS latency of one, two, and three supported
• Auto Precharge command not used
16.2 Overview
The SDRAM Controller (SDRAMC) extends the memory capabilities of a chip by providing the
interface to an external 16-bit SDRAM device. The page size supports ranges from 2048 to 8192
and the number of columns from 256 to 2048. It supports byte (8-bit) and halfword (16-bit)
accesses.
The SDRAMC supports a read or write burst length of one location. It keeps track of the active
row in each bank, thus maximizing SDRAM performance, e.g., the application may be placed in
one bank and data in the other banks. So as to optimize performance, it is advisable to avoid
accessing different rows in the same bank.
The SDRAMC supports a CAS latency of one, two, or three and optimizes the read access
depending on the frequency.
The different modes available (self refresh, power-down, and deep power-down modes) mini-
mize power consumption on the SDRAM device.