Datasheet

207
32072H–AVR32–10/2012
AT32UC3A3
15.6.8 Slow Clock Mode
The SMC is able to automatically apply a set of “slow clock mode” read/write waveforms when
an internal signal driven by the SMC’s Power Management Controller is asserted because
CLK_SMC has been turned to a very slow clock rate (typically 32 kHz clock rate). In this mode,
the user-programmed waveforms are ignored and the slow clock mode waveforms are applied.
This mode is provided so as to avoid reprogramming the User Interface with appropriate wave-
forms at very slow clock rate. When activated, the slow mode is active on all chip selects.
15.6.8.1 Slow clock mode waveforms
Figure 15-30 on page 207 illustrates the read and write operations in slow clock mode. They are
valid on all chip selects. Table 15-5 on page 207 indicates the value of read and write parame-
ters in slow clock mode.
Figure 15-30. Read and Write Cycles in Slow Clock Mode
CLK_SMC
A[AD_MSB:2]
NBS0, NBS1,
A0, A1
NCS
NWE
NWECYCLES = 3
SLOW CLOCK MODE WRITE
1
1
1
CLK_SMC
A[AD_MSB:2]
NBS0, NBS1,
A0, A1
NCS
NRD
SLOW CLOCK MODE READ
NRDCYCLES = 2
1
1
Table 15-5. Read and Write Timing Parameters in Slow Clock Mode
Read Parameters Duration (cycles) Write Parameters Duration (cycles)
NRDSETUP 1 NWESETUP 1
NRDPULSE 1 NWEPULSE 1
NCSRDSETUP 0 NCSWRSETUP 0
NCSRDPULSE 2 NCSWRPULSE 3
NRDCYCLE 2 NWECYCLE 3