Datasheet

204
32072H–AVR32–10/2012
AT32UC3A3
15.6.7.3 Ready mode
In Ready mode (MODE.EXNWMODE = 3), the SMC behaves differently. Normally, the SMC
begins the access by down counting the setup and pulse counters of the read/write controlling
signal. In the last cycle of the pulse phase, the resynchronized NWAIT signal is examined.
If asserted, the SMC suspends the access as shown in Figure 15-27 on page 204 and Figure
15-28 on page 205. After deassertion, the access is completed: the hold step of the access is
performed.
This mode must be selected when the external device uses deassertion of the NWAIT signal to
indicate its ability to complete the read or write operation.
If the NWAIT signal is deasserted before the end of the pulse, or asserted after the end of the
pulse of the controlling read/write signal, it has no impact on the access length as shown in Fig-
ure 15-28 on page 205.
Figure 15-27. NWAIT Assertion in Write Access: Ready Mode (MODE.EXNWMODE = 3).
CLK_SMC
A[AD_MSB:2]
NBS0, NBS1,
A0, A1
NWE
NCS
D[15:0]
654
4
3
3
2
21 0
1
0
11
0
FROZEN STATE
NWAIT
Internally synchronized
NWAIT signal
Write cycle
EXNWMODE = 3 (Ready mode)
WRITEMODE = 1 (NWE_controlled)
NWEPULSE = 5
NCSWRPULSE = 7
0