Datasheet

202
32072H–AVR32–10/2012
AT32UC3A3
The assertion of the NWAIT signal outside the expected period is ignored as illustrated in Figure
15-26 on page 203.
Figure 15-25. Write Access with NWAIT Assertion in Frozen Mode (MODE.EXNWMODE = 2).
CLK_SMC
A[AD_MSB:2]
NBS0, NBS1,
A0, A1
NWE
NCS
D[15:0]
654
4
3
3
2
21 1
2
1
22
1
0
0
FROZEN STATE
NWAIT
Internally synchronized
NWAIT signal
Write cycle
EXNWMODE = 2 (Frozen)
WRITEMODE = 1 (NWE controlled)
NWEPULSE = 5
NCSWRPULSE = 7