195
32072H–AVR32–10/2012
AT32UC3A3
Figure 15-17. Early Read Wait State: NCS Controlled Write with No Hold Followed by a Read
with No Setup.
CLK_SMC
A[AD_MSB:2]
NBS0, NBS1,
A0, A1
NWE
NRD
D[15:0]
No hold
No setup
Read cycle
(READMODE=0 or READMODE=1)
Early Read
Wait State
Write cycle
(WRITEMODE=0)
