Datasheet

194
32072H–AVR32–10/2012
AT32UC3A3
An early read wait state is automatically inserted if at least one of the following conditions is
valid:
• if the write controlling signal has no hold time and the read controlling signal has no setup
time (Figure 15-16 on page 194).
• in NCS write controlled mode (MODE.WRITEMODE = 0), if there is no hold timing on the
NCS signal and the NCSRDSETUP parameter is set to zero, regardless of the read mode
(Figure 15-17 on page 195). The write operation must end with a NCS rising edge. Without
an early read wait state, the write operation could not complete properly.
• in NWE controlled mode (MODE.WRITEMODE = 1) and if there is no hold timing
(NWEHOLD = 0), the feedback of the write control signal is used to control address, data,
chip select, and byte select lines. If the external write control signal is not inactivated as
expected due to load capacitances, an early read wait state is inserted and address, data
and control signals are maintained one more cycle. See Figure 15-18 on page 196.
Figure 15-16. Early Read Wait State: Write with No Hold Followed by Read with No Setup.
CLK_SMC
A[AD_MSB:2]
NBS0, NBS1,
A0, A1
NWE
NRD
D[15:0]
No hold
No setup
Read cycle
Early Read
Wait state
Write cycle