Datasheet

190
32072H–AVR32–10/2012
AT32UC3A3
•Null delay setup and hold
If null setup parameters are programmed for NWE and/or NCS, NWE and/or NCS remain active
continuously in case of consecutive write cycles in the same memory (see Figure 15-12 on page
190). However, for devices that perform write operations on the rising edge of NWE or NCS,
such as SRAM, either a setup or a hold must be programmed.
Figure 15-12. Null Setup and Hold Values of NCS and NWE in Write Cycle
•Null pulse
Programming null pulse is not permitted. Pulse must be at least written to one. A null value leads
to unpredictable behavior.
15.6.4.5 Write mode
The Write Mode bit in the MODE register (MODE.WRITEMODE) of the corresponding chip
select indicates which signal controls the write operation.
•Write is controlled by NWE (MODE.WRITEMODE = 1)
Figure 15-13 on page 191 shows the waveforms of a write operation with MODE.WRITEMODE
equal to one. The data is put on the bus during the pulse and hold steps of the NWE signal. The
internal data buffers are turned out after the NWESETUP time, and until the end of the write
cycle, regardless of the programmed waveform on NCS.
CLK_SMC
A[AD_MSB:2]
NBS0, NBS1,
A0, A1
NWE,
NWE0, NWE1
NCS
NWESETUP NWEPULSE
NCSWRPULSENCSWRSETUP
NWECYCLE
D[15:0]
NWECYCLE
NWEPULSE
NCSWRPULSE
NWECYCLE