Datasheet

182
32072H–AVR32–10/2012
AT32UC3A3
Figure 15-5. Memory Connection for a 16-bit Data Bus
•Byte write access
The byte write access mode supports one byte write signal per byte of the data bus and a single
read signal.
Note that the SMC does not allow boot in byte write access mode.
• For 16-bit devices: the SMC provides NWR0 and NWR1 write signals for respectively byte0
(lower byte) and byte1 (upper byte) of a 16-bit bus. One single read signal (NRD) is provided.
The byte write access mode is used to connect two 8-bit devices as a 16-bit memory.
The byte write option is illustrated on Figure 15-6 on page 183.
•Byte select access
In this mode, read/write operations can be enabled/disabled at a byte level. One byte select line
per byte of the data bus is provided. One NRD and one NWE signal control read and write.
• For 16-bit devices: the SMC provides NBS0 and NBS1 selection signals for respectively
byte0 (lower byte) and byte1 (upper byte) of a 16-bit bus. The byte select access is used to
connect one 16-bit device.
SMC
NBS0
NWE
NRD
NCS[2]
Low Byte Enable
Write Enable
Output Enable
Memory Enable
NBS1 High Byte Enable
D[15:0] D[15:0]
A[19:2]
A[18:1]
A[0]A1