Datasheet

176
32072H–AVR32–10/2012
AT32UC3A3
Note: 1. Not directly connected to the CompactFlash slot. Permits the control of the bidirectional buffer
between the EBI data bus and the CompactFlash slot.
2. Any I/O Controller line.
3. The CLE and ALE signals of the NAND Flash device may be driven by any address bit. For
details, see Section 14.6.6.
ADDR[21] – – CLE
(3)
ADDR[22] – REG ALE
(3)
NCS[0] – – –
NCS[1] SDCS[0] – –
NCS[2] – – CE0
NCS[3] – – CE1
NCS[4] – CFCS0
(1)
–
NCS[5] – CFCS1
(1)
–
NANDOE – – OE
NANDWE – – WE
NRD – OE –
NWE0 – WE –
NWE1 DQM1 IOR –
CFRNW – CFRNW
(1)
–
CFCE1 – CE1 –
CFCE2 – CE2 –
SDCK CLK – –
SDCKE CKE – –
RAS RAS – –
CAS CAS – –
SDWE WE – –
NWAIT – WAIT –
Pxx
(2)
– CD1 or CD2 –
Pxx
(2)
––RDY
Table 14-10. EBI Pins and External Devices Connections (Continued)
Pins name
Pins of the Interfaced Device
SDRAM
Compact
Flash
Smart Media
or
NAND Flash
Controller SDRAMC SMC