Datasheet

139
32072H–AVR32–10/2012
AT32UC3A3
12.8 User interface
12.8.1 Address map
The following addresses are used by the None. All offsets are relative to the base address allo-
cated to the flash controller.
(*) The value of the Lock bits is dependent of their programmed state. All other bits in FSR are 0.
All bits in FGPFR and FCFR are dependent on the programmed state of the fuses they map to.
Any bits in these registers not mapped to a fuse read 0.
Table 12-4. Flash controller register mapping
Offset Register Name Access
Reset
state
0x0 Flash Control Register FCR R/W 0
0x4 Flash Command Register FCMD R/W 0
0x8 Flash Status Register FSR R/W 0 (*)
0xc Flash General Purpose Fuse Register Hi FGPFRHI R NA (*)
0x10 Flash General Purpose Fuse Register Lo FGPFRLO R NA (*)