Features • High Performance, Low Power 32-bit Atmel® AVR® Microcontroller • • • • • • • • • • • • – Compact Single-Cycle RISC Instruction Set Including DSP Instruction Set – Read-Modify-Write Instructions and Atomic Bit Manipulation – Performing up to 1.
AT32UC3A3 • • • • • • • • • – Support for SPI and LIN – Optionnal support for IrDA, ISO7816, Hardware Handshaking, RS485 interfaces and Modem Line Two Master/Slave Serial Peripheral Interfaces (SPI) with Chip Select Signals One Synchronous Serial Protocol Controller – Supports I2S and Generic Frame-Based Protocols Two Master/Slave Two-Wire Interface (TWI), 400kbit/s I2C-compatible 16-bit Stereo Audio Bitstream – Sample Rate Up to 50 KHz QTouch® Library Support – Capacitive Touch Buttons, Sliders, and W
AT32UC3A3 1. Description The AT32UC3A3/A4 is a complete System-On-Chip microcontroller based on the AVR32 UC RISC processor running at frequencies up to 84MHz. AVR32 UC is a high-performance 32-bit RISC microprocessor core, designed for cost-sensitive embedded applications, with particular emphasis on low power consumption, high code density and high performance.
AT32UC3A3 2. Overview Block Diagram NEXUS CLASS 2+ OCD MCKO MDO[5..0] MSEO[1..
AT32UC3A3 2.2 Configuration Summary The table below lists all AT32UC3A3/A4 memory and package configurations: Table 2-1.
AT32UC3A3 3. Package and Pinout 3.1 Package The device pins are multiplexed with peripheral functions as described in the Peripheral Multiplexing on I/O Line section. Figure 3-1.
AT32UC3A3 LQFP144 Pinout 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 TDI TCK RESET_N TDO TMS VDDIO GNDIO PA15 PA14 PC01 PC00 PX31 PX30 PX33 PX29 PX32 PX25 PX28 PX26 PX27 PX43 PX52 PX24 PX23 PX18 PX17 GNDIO VDDIO PX21 PX55 PX56 PX51 PX57 PX50 PX46 PX20 Figure 3-2.
AT32UC3A3 Figure 3-3.
AT32UC3A3 3.2 Peripheral Multiplexing on I/O lines 3.2.1 Multiplexed Signals Each GPIO line can be assigned to one of the peripheral functions. The following table describes the peripheral signals multiplexed to the GPIO lines. Note that GPIO 44 is physically implemented in silicon but it must be kept unused and configured in input mode. Table 3-1.
AT32UC3A3 Table 3-1.
AT32UC3A3 Table 3-1.
AT32UC3A3 Table 3-1. GPIO Controller Function Multiplexing GPIO function G P BGA QFP BGA 144 144 100 J4 PIN I Type PIN O Supply (2) A B C 78 PX56 107 VDDIO x2 EBI - ADDR[21] EIC - SCAN[2] USART2 - TXD H4 76 PX57 108 VDDIO x2 EBI - ADDR[20] EIC - SCAN[1] USART3 - RXD H3 57 EIC - SCAN[0] USART3 - TXD G3 56 F1(1) PX58 109 VDDIO x2 EBI - NCS[0] PX59 110 VDDIO x2 EBI - NANDWE Note: D MCI - CMD[1] 1. Those balls are physically connected to 2 GPIOs.
AT32UC3A3 3.2.4 JTAG port connections Table 3-4. 3.2.5 JTAG Pinout TFBGA144 QFP144 VFBGA100 Pin name JTAG pin K12 107 K9 TCK TCK L12 108 K8 TDI TDI J11 105 J8 TDO TDO J10 104 H7 TMS TMS Nexus OCD AUX port connections If the OCD trace system is enabled, the trace system will take control over a number of pins, irrespective of the GPIO configuration. Three differents OCD trace pin mappings are possible, depending on the configuration of the OCD AXS register.
AT32UC3A3 3.3 Signal Descriptions The following table gives details on signal name classified by peripheral. Table 3-6. Signal Description List Signal Name Function Type Active Level Comments Power VDDIO I/O Power Supply Power 3.0 to 3.6V VDDANA Analog Power Supply Power 3.0 to 3.6V VDDIN Voltage Regulator Input Supply Power 3.0 to 3.6V VDDCORE Voltage Regulator Output for Digital Supply Power Output 1.65 to 1.
AT32UC3A3 Table 3-6.
AT32UC3A3 Table 3-6.
AT32UC3A3 Table 3-6.
AT32UC3A3 Table 3-6. Signal Description List Signal Name Function Type DMHS USB High Speed Data - Analog DPHS USB High Speed Data + Analog USB_VBIAS USB VBIAS reference Analog USB_VBUS USB VBUS signal Output VBOF USB VBUS on/off bus power control port Output ID ID Pin fo the USB bus Active Level Comments Connect to the ground through a 6810 ohms (+/- 1%) resistor in parallel with a 10pf capacitor.
AT32UC3A3 3.4 3.4.1 I/O Line Considerations JTAG Pins TMS and TDI pins have pull-up resistors. TDO pin is an output, driven at up to VDDIO, and has no pull-up resistor. 3.4.2 RESET_N Pin The RESET_N pin is a schmitt input and integrates a permanent pull-up resistor to VDDIO. As the product integrates a power-on reset cell, the RESET_N pin can be left unconnected in case no reset from the system needs to be applied to the product. 3.4.
AT32UC3A3 3.5 3.5.1 Power Considerations Power Supplies The AT32UC3A3 has several types of power supply pins: • • • • VDDIO: Powers I/O lines. Voltage is 3.3V nominal VDDANA: Powers the ADC. Voltage is 3.3V nominal VDDIN: Input voltage for the voltage regulator. Voltage is 3.3V nominal VDDCORE: Output voltage from regulator for filtering purpose and provides the supply to the core, memories, and peripherals. Voltage is 1.8V nominal The ground pin GNDCORE is common to VDDCORE and VDDIN.
AT32UC3A3 4. Processor and Architecture Rev: 1.4.2.0 This chapter gives an overview of the AVR32UC CPU. AVR32UC is an implementation of the AVR32 architecture. A summary of the programming model, instruction set, and MPU is presented. For further details, see the AVR32 Architecture Manual and the AVR32UC Technical Reference Manual. 4.
AT32UC3A3 The register file is organized as sixteen 32-bit registers and includes the Program Counter, the Link Register, and the Stack Pointer. In addition, register R12 is designed to hold return values from function calls and is used implicitly by some instructions. 4.3 The AVR32UC CPU The AVR32UC CPU targets low- and medium-performance applications, and provides an advanced OCD system, no caches, and a Memory Protection Unit (MPU). Java acceleration hardware is not implemented.
AT32UC3A3 OCD interface Reset interface Overview of the AVR32UC CPU Interrupt controller interface Figure 4-1. OCD system Power/ Reset control AVR32UC CPU pipeline MPU 4.3.
AT32UC3A3 Figure 4-2. The AVR32UC Pipeline Multiply unit MUL IF ID Pref etch unit Decode unit Regf ile Read A LU LS 4.3.2 Regf ile w rite A LU unit Load-store unit AVR32A Microarchitecture Compliance AVR32UC implements an AVR32A microarchitecture. The AVR32A microarchitecture is targeted at cost-sensitive, lower-end applications like smaller microcontrollers. This microarchitecture does not provide dedicated hardware registers for shadowing of register file registers in interrupt contexts.
AT32UC3A3 The following table shows the instructions with support for unaligned addresses. All other instructions require aligned addresses. Table 4-1. 4.3.6 Instructions with Unaligned Reference Support Instruction Supported alignment ld.d Word st.
AT32UC3A3 4.4 4.4.1 Programming Model Register File Configuration The AVR32UC register file is shown below. Figure 4-3.
AT32UC3A3 Figure 4-5. The Status Register Low Halfword Bit 15 Bit 0 - T - - - - - - - - L Q V N Z C Bit name 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Initial value Carry Zero Sign Overflow Saturation Lock Reserved Scratch Reserved 4.4.3 4.4.3.1 Processor States Normal RISC State The AVR32 processor supports several different execution contexts as shown in Table 4-2 on page 27. Table 4-2. Overview of Execution Modes, their Priorities and Privilege Levels.
AT32UC3A3 All interrupt levels are by default disabled when debug state is entered, but they can individually be switched on by the monitor routine by clearing the respective mask bit in the status register. Debug state can be entered as described in the AVR32UC Technical Reference Manual. Debug state is exited by the retd instruction. 4.4.4 System Registers The system registers are placed outside of the virtual memory space, and are only accessible using the privileged mfsr and mtsr instructions.
AT32UC3A3 Table 4-3.
AT32UC3A3 Table 4-3. 4.
AT32UC3A3 The user must also make sure that the system stack is large enough so that any event is able to push the required registers to stack. If the system stack is full, and an event occurs, the system will enter an UNDEFINED state. 4.5.2 Exceptions and Interrupt Requests When an event other than scall or debug request is received by the core, the following actions are performed atomically: 1. The pending event will not be accepted if it is masked.
AT32UC3A3 status register. Upon entry into Debug mode, hardware sets the SR[D] bit and jumps to the Debug Exception handler. By default, Debug mode executes in the exception context, but with dedicated Return Address Register and Return Status Register. These dedicated registers remove the need for storing this data to the system stack, thereby improving debuggability.
AT32UC3A3 Table 4-4.
AT32UC3A3 4.6 Module Configuration All AT32UC3A3 parts implement the CPU and Architecture Revision 2.
AT32UC3A3 5. Memories 5.
AT32UC3A3 Table 5-1. 5.3 AT32UC3A3A4 Physical Memory Map Size Size Size Device Start Address AT32UC3A3256S AT32UC3A3256 AT32UC3A4256S AT32UC3A4256 AT32UC3A3128S AT32UC3A3128 AT32UC3A4128S AT32UC3A4128 AT32UC3A364S AT32UC3A364 AT32UC3A464S AT32UC3A464 HRAMC0 0xFF000000 32KByte 32KByte 32KByte HRAMC1 0xFF008000 32KByte 32KByte 32KByte HSB-PB Bridge A 0xFFFF0000 64KByte 64KByte 64KByte HSB-PB Bridge B 0xFFFE0000 64KByte 64KByte 64KByte Peripheral Address Map Table 5-2.
AT32UC3A3 Table 5-2.
AT32UC3A3 Table 5-2. Peripheral Address Mapping 0xFFFF5000 TWIS0 Two-wire Slave Interface - TWIS0 TWIS1 Two-wire Slave Interface - TWIS1 0xFFFF5400 5.4 CPU Local Bus Mapping Some of the registers in the GPIO module are mapped onto the CPU local bus, in addition to being mapped on the Peripheral Bus. These registers can therefore be reached both by accesses on the Peripheral Bus, and by accesses on the local bus.
AT32UC3A3 Table 5-3.
AT32UC3A3 6. Boot Sequence This chapter summarizes the boot sequence of the AT32UC3A3/A4. The behavior after powerup is controlled by the Power Manager. For specific details, refer to Section 7. ”Power Manager (PM)” on page 41. 6.1 Starting of Clocks After power-up, the device will be held in a reset state by the Power-On Reset circuitry, until the power has stabilized throughout the device. Once the power has stabilized, the device will use the internal RC Oscillator as clock source.
AT32UC3A3 7. Power Manager (PM) Rev: 2.3.1.0 7.1 Features • • • • • • • • • • • • • 7.2 Controls integrated oscillators and PLLs Generates clocks and resets for digital logic Supports 2 crystal oscillators 0.
AT32UC3A3 7.3 Block Diagram Figure 7-1.
AT32UC3A3 7.4 7.4.1 Product Dependencies I/O Lines The PM provides a number of generic clock outputs, which can be connected to output pins, multiplexed with I/O lines. The user must first program the I/O controller to assign these pins to their peripheral function. If the I/O pins of the PM are not used by the application, they can be used for other purposes by the I/O controller. 7.4.2 Interrupt The PM interrupt line is connected to one of the internal sources of the interrupt controller.
AT32UC3A3 Figure 7-2. Oscillator Connections C2 XO UT XIN C1 7.5.3 32 KHz Oscillator Operation The 32 KHz oscillator operates as described for Oscillator 0 and 1 above. The 32 KHz oscillator is used as source clock for the Real-Time Counter. The oscillator is disabled by default, but can be enabled by writing OSC32EN in OSCCTRL32. The oscillator is an ultra-low power design and remains enabled in all sleep modes except Static mode.
AT32UC3A3 Figure 7-3. PLL with Control Logic and Filters PLLMUL Output Divider Osc0 clock Osc1 clock 0 Input Divider 1 PLLOSC 7.5.4.1 Fin PLLDIV PLL Mask PLL clock LOCK PLLEN PLLOPT Enabling the PLL PLLn is enabled by writing the PLLEN bit in the PLLn register. PLLOSC selects Oscillator 0 or 1 as clock source.
AT32UC3A3 The PLLn:PLLOPT field should be set to proper values according to the PLL operating frequency. The PLLOPT field can also be set to divide the output frequency of the PLLs by 2. The lock signal for each PLL is available as a LOCKn flag in POSCSR. An interrupt can be generated on a 0 to 1 transition of these bits. 7.5.
AT32UC3A3 7.5.5.2 Selecting synchronous clock division ratio The main clock feeds an 8-bit prescaler, which can be used to generate the synchronous clocks. By default, the synchronous clocks run on the undivided main clock. The user can select a prescaler division for the CPU clock by writing CKSEL.
AT32UC3A3 7.5.6.2 7.5.7 Mask ready flag Due to synchronization in the clock generator, there is a slight delay from a mask register is written until the new mask setting goes into effect. When clearing mask bits, this delay can usually be ignored. However, when setting mask bits, the registers in the corresponding module must not be written until the clock has actually be re-enabled. The status flag MSKRDY in ISR provides the required mask status information.
AT32UC3A3 Table 7-1.
AT32UC3A3 Each generic clock module runs from either Oscillator 0 or 1, or PLL0 or 1. The selected source can optionally be divided by any even integer up to 512. Each clock can be independently enabled and disabled, and is also automatically disabled along with peripheral clocks by the Sleep Controller. Figure 7-5. Generic Clock Generation Sleep Controller 0 Osc0 clock Osc1 clock PLL0 clock PLL1 clock Divider Generic Clock 1 1 PLLSEL OSCSEL 7.5.8.
AT32UC3A3 7.5.8.4 Generic clock implementation The generic clocks are allocated to different functions as shown in Table 7-2 on page 51. Table 7-2. 7.5.9 Generic Clock Allocation Clock number Function 0 GCLK0 pin 1 GCLK1 pin 2 GCLK2 pin 3 GCLK3 pin 4 GCLK_USBB 5 GCLK_ABDAC Divided PB Clocks The clock generator in the Power Manager provides divided PBA and PBB clocks for use by peripherals that require a prescaled PBx clock. This is described in the documentation for the relevant modules.
AT32UC3A3 Figure 7-6. Reset Controller Block Diagram R C _R CAU SE RESET_N CPU, HSB, PBA, PBB P o w e r-O n D e te c to r R eset C o n tro lle r B ro w n o u t D e te c to r O C D , R T C /W D T , C lo c k G e n e ra to r JTA G OCD WDT In addition to the listed reset types, the JTAG can keep parts of the device statically reset through the JTAG Reset Register. See JTAG documentation for details. Table 7-3.
AT32UC3A3 Table 7-4 on page 53 lists parts of the device that are reset, depending on the reset source. Table 7-4.
AT32UC3A3 7.5.11.3 Brown-Out detector 3V3 The Brown-Out Detector 3V3 (BOD33) monitors one VDDIO supply pin and compares the supply voltage to the brown-out detection 3V3 level, which is typically calibrated at 2V7. The BOD33 is enabled by default, but can be disabled by software. The Brown-Out Detector 3V3 can either generate an interrupt or a reset when the supply voltage is below the brown-out detection3V3 level. In any case, the BOD33 output is available in bit POSCSR.BOD33DET bit.
AT32UC3A3 7.6 User Interface Table 7-6.
AT32UC3A3 7.6.
AT32UC3A3 7.6.2 Name: Clock Select Register CKSEL Access Type: Read/Write Offset: 0x04 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 PBBDIV - - - - 23 22 21 20 19 PBADIV - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 CPUDIV - - - - PBBSEL 18 17 16 PBASEL CPUSEL • PBBDIV: PBB Division Enable PBBDIV = 0: PBB clock equals main clock. PBBDIV = 1: PBB clock equals main clock divided by 2(PBBSEL+1).
AT32UC3A3 7.6.3 Name: Clock Mask Registers CPU/HSB/PBA/PBBMASK Access Type: Read/Write Offset: 0x08-0x14 Reset Value: 0x00000003/0x00000FFF/0x001FFFFF/0x000003FF 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 MASK[31:24] 23 22 21 20 MASK[23:16] 15 14 13 12 MASK[15:8] 7 6 5 4 MASK[7:0] • MASK: Clock Mask If bit n is written to zero, the clock for module n is stopped.
AT32UC3A3 Table 7-7. Maskable module clocks in AT32UC3A3. Bit CPUMASK HSBMASK PBAMASK PBBMASK 16 SYSTIMER (compare/count registers clk) - TC0 - 17 - - TC1 - 18 - - ABDAC - - (2) - 19 - 20 - - (2) 31:21 - - - Note: 1. This bit must be set to one if the user wishes to debug the device with a JTAG debugger. 2.
AT32UC3A3 7.6.4 Name: PLL Control Registers PLL0,1 Access Type: Read/Write Offset: 0x20-0x24 Reset Value: 0x00000000 31 30 29 28 PLLTEST - 23 22 21 20 - - - - 15 14 13 12 - - - - 7 6 5 4 - - - 27 26 25 24 18 17 16 9 8 1 0 PLLOSC PLLEN PLLCOUNT 19 PLLMUL 11 10 PLLDIV 3 PLLOPT 2 • PLLTEST: PLL Test Reserved for internal use. Always write to 0. • PLLCOUNT: PLL Count Specifies the number of slow clock cycles before ISR.
AT32UC3A3 • PLLEN: PLL Enable 0: PLL is disabled. 1: PLL is enabled.
AT32UC3A3 7.6.5 Name: Oscillator 0/1 Control Registers OSCCTRL0,1 Access Type: Read/Write Offset: 0x28-0x2C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - 7 6 5 4 3 - - - - - STARTUP 2 1 0 MODE • STARTUP: Oscillator Startup Time Select startup time for the oscillator.
AT32UC3A3 7.6.
AT32UC3A3 7.6.7 Name: Interrupt Enable Register IER Access Type: Write-only Offset: 0x40 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - BOD33DET BODDET 15 14 13 12 11 10 9 8 - - - - - - OSC32RDY OSC1RDY 7 6 5 4 3 2 1 0 OSC0RDY MSKRDY CKRDY - - - LOCK1 LOCK0 Writing a one to a bit in this register will set the corresponding bit in IMR.
AT32UC3A3 7.6.8 Name: Interrupt Disable Register IDR Access Type: Write-only Offset: 0x44 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - BOD33DET BODDET 15 14 13 12 11 10 9 8 - - - - - - OSC32RDY OSC1RDY 7 6 5 4 3 2 1 0 OSC0RDY MSKRDY CKRDY - - - LOCK1 LOCK0 Writing a one to a bit in this register will clear the corresponding bit in IMR.
AT32UC3A3 7.6.9 Name: Interrupt Mask Register IMR Access Type: Read-only Offset: 0x48 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - BOD33DET BODDET 15 14 13 12 11 10 9 8 - - - - - - OSC32RDY OSC1RDY 7 6 5 4 3 2 1 0 OSC0RDY MSKRDY CKRDY - - - LOCK1 LOCK0 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled.
AT32UC3A3 7.6.10 Name: Interrupt Status Register ISR Access Type: Read-only Offset: 0x4C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - BOD33DET BODDET 15 14 13 12 11 10 9 8 - - - - - - OSC32RDY OSC1RDY 7 6 5 4 3 2 1 0 OSC0RDY MSKRDY CKRDY - - - LOCK1 LOCK0 • BOD33DET: Brown out detection This bit is set when a 0 to 1 transition on POSCSR.
AT32UC3A3 • LOCK1: PLL1 locked This bit is set when a 0 to 1 transition on the POSCSR.LOCK1 bit is detected: PLL 1 is locked and ready to be selected as clock source. This bit is cleared when the corresponding bit in ICR is written to one. • LOCK0: PLL0 locked This bit is set when a 0 to 1 transition on the POSCSR.LOCK0 bit is detected: PLL 0 is locked and ready to be selected as clock source. This bit is cleared when the corresponding bit in ICR is written to one.
AT32UC3A3 7.6.11 Name: Interrupt Clear Register ICR Access Type: Write-only Offset: 0x50 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - BOD33DET BODDET 15 14 13 12 11 10 9 8 - - - - - - OSC32RDY OSC1RDY 7 6 5 4 3 2 1 0 OSC0RDY MSKRDY CKRDY - - - LOCK1 LOCK0 Writing a zero to a bit in this register has no effect.
AT32UC3A3 7.6.
AT32UC3A3 7.6.13 Name: Generic Clock Control Register GCCTRLx Access Type: Read/Write Offset: 0x60 - 0x74 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 DIV[7:0] 7 6 5 4 3 2 1 0 - - - DIVEN - CEN PLLSEL OSCSEL There is one GCCTRL register per generic clock in the design.
AT32UC3A3 7.6.14 Name: RC Oscillator Calibration Register RCCR Access Type: Read/Write Offset: 0xC0 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 KEY 23 22 21 20 19 18 17 16 - - - - - - - FCD 15 14 13 12 11 10 9 8 - - - - - - 7 6 5 4 3 2 CALIB 1 0 CALIB • KEY: Register Write protection This field must be written twice, first with key value 0x55, then 0xAA, for a write operation to have an effect.
AT32UC3A3 7.6.15 Name: Bandgap Calibration Register BGCR Access Type: Read/Write Offset: 0xC4 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 KEY 23 22 21 20 19 18 17 16 - - - - - - - FCD 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - CALIB • KEY: Register Write protection This field must be written twice, first with key value 0x55, then 0xAA, for a write operation to have an effect.
AT32UC3A3 7.6.16 Name: PM Voltage Regulator Calibration Register VREGCR Access Type: Read/Write Offset: 0xC8 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 KEY 23 22 21 20 19 18 17 16 - - - - - - - FCD 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - CALIB • KEY: Register Write protection This field must be written twice, first with key value 0x55, then 0xAA, for a write operation to have an effect.
AT32UC3A3 7.6.17 Name: BOD Control Register BOD Access Type: Read/Write Offset: 0xD0 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 KEY 23 22 21 20 19 18 17 16 - - - - - - - FCD 15 14 13 12 11 10 9 8 - - - - - - 7 6 5 4 3 2 - HYST CTRL 1 0 LEVEL • KEY: Register Write protection This field must be written twice, first with key value 0x55, then 0xAA, for a write operation to have an effect.
AT32UC3A3 7.6.18 Name: BOD33 Control Register BOD33 Access Type: Read/Write Offset: 0xD4 Reset Value: 0x0000010X 31 30 29 28 27 26 25 24 KEY 23 22 21 20 19 18 17 16 - - - - - - - FCD 15 14 13 12 11 10 9 8 - - - - - - 7 6 5 4 3 2 - - CTRL 1 0 LEVEL • KEY: Register Write protection This field must be written twice, first with key value 0x55, then 0xAA, for a write operation to have an effect.
AT32UC3A3 7.6.19 Name: Reset Cause Register RCAUSE Access Type: Read-only Offset: 0x140 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - BOD33 - OCDRST 7 6 5 4 3 2 1 0 CPUERR - - JTAG WDT EXT BOD POR • BOD33: Brown-out 3V3 Reset The CPU was reset due to the supply voltage 3V3 being lower than the brown-out threshold level.
AT32UC3A3 7.6.20 Asynchronous Wake Up Enable Name: AWEN Access Type: Read/Write Offset: 0x144 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - USB_WAKEN • USB_WAKEN : Wake Up Enable Register Writing a zero to this bit will disable the USB wake up. Writing a one to this bit will enable the USB wake up.
AT32UC3A3 7.6.21 Name: General Purpose Low-power Register GPLP Access Type: Read/Write Offset: 0x200 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 GPLP 23 22 21 20 GPLP 15 14 13 12 GPLP 7 6 5 4 GPLP These registers are general purpose 32-bit registers that are reset only by power-on-reset. Any other reset will keep the content of these registers untouched.
AT32UC3A3 8. Real Time Counter (RTC) Rev: 2.4.0.1 8.1 Features • 32-bit real-time counter with 16-bit prescaler • Clocked from RC oscillator or 32KHz oscillator • Long delays • • • • 8.2 – Max timeout 272years High resolution: Max count frequency 16KHz Extremely low power consumption Available in all sleep modes except Static Interrupt on wrap Overview The Real Time Counter (RTC) enables periodic interrupts at long intervals, or accurate measurement of real-time sequences.
AT32UC3A3 8.4.1 Power Management The RTC remains operating in all sleep modes except Static mode. Interrupts are not available in DeepStop mode. 8.4.2 Clocks The RTC can use the system RC oscillator as clock source. This oscillator is always enabled whenever this module is active. Please refer to the Electrical Characteristics chapter for the characteristic frequency of this oscillator (fRC). The RTC can also use the 32 KHz crystal oscillator as clock source. This oscillator must be enabled before use.
AT32UC3A3 The RTC count value can be read from or written to the Value register (VAL). Due to synchronization, continuous reading of the VAL register with the lowest prescaler setting will skip every other value. 8.5.1.3 RTC interrupt The RTC interrupt is enabled by writing a one to the Top Interrupt bit in the Interrupt Enable Register (IER.TOPI), and is disabled by writing a one to the Top Interrupt bit in the Interrupt Disable Register (IDR.TOPI).
AT32UC3A3 8.6 User Interface Table 8-1.
AT32UC3A3 8.6.1 Name: Control Register CTRL Access Type: Read/Write Offset: 0x00 Reset Value: 0x00010000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - CLKEN 15 14 13 12 11 10 9 8 - - - - 7 6 5 4 3 2 1 0 - - - BUSY CLK32 WAKEN PCLR EN PSEL • CLKEN: Clock Enable 1: The clock is enabled. 0: The clock is disabled. • PSEL: Prescale Select Selects prescaler bit PSEL as source clock for the RTC.
AT32UC3A3 8.6.2 Name: Value Register VAL Access Type: Read/Write Offset: 0x04 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 VAL[31:24] 23 22 21 20 VAL[23:16] 15 14 13 12 VAL[15:8] 7 6 5 4 VAL[7:0] • VAL[31:0]: RTC Value This value is incremented on every rising edge of the source clock.
AT32UC3A3 8.6.3 Name: Top Register TOP Access Type: Read/Write Offset: 0x08 Reset Value: 0xFFFFFFFF 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 VAL[31:24] 23 22 21 20 VAL[23:16] 15 14 13 12 VAL[15:8] 7 6 5 4 VAL[7:0] • VAL[31:0]: RTC Top Value VAL wraps at this value.
AT32UC3A3 8.6.4 Name: Interrupt Enable Register IER Access Type: Write-only Offset: 0x10 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - TOPI Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR.
AT32UC3A3 8.6.5 Name: Interrupt Disable Register IDR Access Type: Write-only Offset: 0x14 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - TOPI Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR.
AT32UC3A3 8.6.6 Name: Interrupt Mask Register IMR Access Type: Read-only Offset: 0x18 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - TOPI 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. A bit in this register is cleared when the corresponding bit in IDR is written to one.
AT32UC3A3 8.6.7 Name: Interrupt Status Register ISR Access Type: Read-only Offset: 0x1C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - TOPI • TOPI: Top Interrupt This bit is set when VAL has wrapped at its top value. This bit is cleared when the corresponding bit in ICR is written to one.
AT32UC3A3 8.6.8 Name: Interrupt Clear Register ICR Access Type: Write-only Offset: 0x20 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - TOPI Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in SR and the corresponding interrupt request.
AT32UC3A3 9. Watchdog Timer (WDT) Rev: 2.4.0.1 9.1 Features • Watchdog timer counter with 32-bit prescaler • Clocked from the system RC oscillator (RCSYS) 9.2 Overview The Watchdog Timer (WDT) has a prescaler generating a time-out period. This prescaler is clocked from the RC oscillator. The watchdog timer must be periodically reset by software within the time-out period, otherwise, the device is reset and starts executing from the boot vector.
AT32UC3A3 9.5 Functional Description The WDT is enabled by writing a one to the Enable bit in the Control register (CTRL.EN). This also enables the system RC clock (CLK_RCSYS) for the prescaler. The Prescale Select field (PSEL) in the CTRL register selects the watchdog time-out period: TWDT = 2(PSEL+1) / fRC The next time-out period will begin as soon as the watchdog reset has occurred and count down during the reset sequence.
AT32UC3A3 9.6.1 Name: Control Register CTRL Access Type: Read/Write Offset: 0x00 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 KEY 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - 7 6 5 4 3 2 1 0 - - - - - - - EN PSEL • KEY: Write protection key This field must be written twice, first with key value 0x55, then 0xAA, for a write operation to be effective. This field always reads as zero.
AT32UC3A3 9.6.2 Name: Clear Register CLR Access Type: Write-only Offset: 0x04 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CLR[31:24] 23 22 21 20 CLR[23:16] 15 14 13 12 CLR[15:8] 7 6 5 4 CLR[7:0] • CLR: Writing periodically any value to this field when the WDT is enabled, within the watchdog time-out period, will prevent a watchdog reset. This field always reads as zero.
AT32UC3A3 10. Interrupt Controller (INTC) Rev: 1.0.1.5 10.1 Features • Autovectored low latency interrupt service with programmable priority – 4 priority levels for regular, maskable interrupts – One Non-Maskable Interrupt • Up to 64 groups of interrupts with up to 32 interrupt requests in each group 10.2 Overview The INTC collects interrupt requests from the peripherals, prioritizes them, and delivers an interrupt request and an autovector to the CPU.
AT32UC3A3 Figure 10-1. INTC Block Diagram Interrupt Controller CPU NMIREQ Masks OR IRRn GrpReqN IREQ63 IREQ34 IREQ33 IREQ32 OR GrpReq1 INT_level, offset IPRn . . . Request Masking ValReq1 INT_level, offset IPR1 . . . INTLEVEL Prioritizer . . . ValReqN SREG Masks I[3-0]M GM AUTOVECTOR IRR1 IREQ31 IREQ2 IREQ1 IREQ0 OR GrpReq0 ValReq0 IPR0 INT_level, offset IRR0 IRR Registers 10.
AT32UC3A3 Interrupt Priority Register (IPR). The GrpReq inputs are then masked by the mask bits from the CPU status register. Any interrupt group that has a pending interrupt of a priority level that is not masked by the CPU status register, gets its corresponding ValReq line asserted. Masking of the interrupt requests is done based on five interrupt mask bits of the CPU status register, namely Interrupt Level 3 Mask (I3M) to Interrupt Level 0 Mask (I0M), and Global Interrupt Mask (GM).
AT32UC3A3 pipeline stall, which prevents the interrupt from accidentally re-triggering in case the handler is exited and the interrupt mask is cleared before the interrupt request is cleared.
AT32UC3A3 10.6 User Interface Table 10-1. INTC Register Memory Map Offset Register Register Name Access Reset 0x000 Interrupt Priority Register 0 IPR0 Read/Write 0x00000000 0x004 Interrupt Priority Register 1 IPR1 Read/Write 0x00000000 ... ... ... ... ... 0x0FC Interrupt Priority Register 63 IPR63 Read/Write 0x00000000 0x100 Interrupt Request Register 0 IRR0 Read-only N/A 0x104 Interrupt Request Register 1 IRR1 Read-only N/A ... ... ... ... ...
AT32UC3A3 10.6.1 Name: Interrupt Priority Registers IPR0...
AT32UC3A3 10.6.2 Name: Interrupt Request Registers IRR0...
AT32UC3A3 10.6.3 Name: Interrupt Cause Registers ICR0...ICR3 Access Type: Read-only Offset: 0x200 - 0x20C Reset Value: N/A 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - CAUSE • CAUSE: Interrupt Group Causing Interrupt of Priority n ICRn identifies the group with the highest priority that has a pending interrupt of level n.
AT32UC3A3 10.7 Interrupt Request Signal Map The various modules may output Interrupt request signals. These signals are routed to the Interrupt Controller (INTC), described in a later chapter. The Interrupt Controller supports up to 64 groups of interrupt requests. Each group can have up to 32 interrupt request signals. All interrupt signals in the same group share the same autovector address and priority level.
AT32UC3A3 Table 10-2.
AT32UC3A3 Table 10-2.
AT32UC3A3 11. External Interrupt Controller (EIC) Rev: 2.4.0.0 11.1 Features • • • • • • • • 11.2 Dedicated interrupt request for each interrupt Individually maskable interrupts Interrupt on rising or falling edge Interrupt on high or low level Asynchronous interrupts for sleep modes without clock Filtering of interrupt lines Maskable NMI interrupt Keypad scan support Overview The External Interrupt Controller (EIC) allows pins to be configured as external interrupts.
AT32UC3A3 11.3 Block Diagram Figure 11-1. EIC Block Diagram EN D IS E n a b le LEVEL MODE EDGE ASYNC P o la r it y c o n tro l A s y n c h ro n u s d e te c to r F IL T E R LEVEL MODE EDGE F ilt e r E d g e /L e v e l D e te c to r E X T IN T n NMI CTRL IC R CTRL IE R ID R IN T n M ask IS R IM R W ake d e te c t CLK_SYN C IR Q n E IC _ W A K E CLK_RC SYS P r e s c a le r S h if t e r PRESC SCANm P IN EN SCAN 11.4 I/O Lines Description Table 11-1. 11.
AT32UC3A3 11.5.3 Clocks The clock for the EIC bus interface (CLK_EIC) is generated by the Power Manager. This clock is enabled at reset, and can be disabled in the Power Manager. The filter and synchronous edge/level detector runs on a clock which is stopped in any of the sleep modes where the system RC oscillator is not running. This clock is referred to as CLK_SYNC. Refer to the Module Configuration section at the end of this chapter for details.
AT32UC3A3 gate to the interrupt controller. However, the corresponding bit in ISR will be set, and EIC_WAKE will be set. If the CTRL.INTn bit is zero, then the corresponding bit in ISR will always be zero. Disabling an external interrupt by writing to the DIS.INTn bit will clear the corresponding bit in ISR. 11.6.
AT32UC3A3 11.6.3 Non-Maskable Interrupt The NMI supports the same features as the external interrupts, and is accessed through the same registers. The description in Section 11.6.1 should be followed, accessing the NMI bit instead of the INTn bits. The NMI is non-maskable within the CPU in the sense that it can interrupt any other execution mode. Still, as for the other external interrupts, the actual NMI input can be enabled and disabled by accessing the registers in the EIC. 11.6.
AT32UC3A3 11.6.6 Keypad scan support The External Interrupt Controller also includes support for keypad scanning. The keypad scan feature is compatible with keypads organized as rows and columns, where a row is shorted against a column when a key is pressed. The rows should be connected to the external interrupt pins with pull-ups enabled in the I/O Controller. These external interrupts should be enabled as low level or falling edge interrupts. The columns should be connected to the available scan pins.
AT32UC3A3 11.7 User Interface Table 11-2.
AT32UC3A3 11.7.1 Name: Interrupt Enable Register IER Access Type: Write-only Offset: 0x000 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - NMI 7 6 5 4 3 2 1 0 INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0 • INTn: External Interrupt n Writing a zero to this bit has no effect. Writing a one to this bit will set the corresponding bit in IMR.
AT32UC3A3 11.7.2 Name: Interrupt Disable Register IDR Access Type: Write-only Offset: 0x004 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - NMI 7 6 5 4 3 2 1 0 INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0 • INTn: External Interrupt n Writing a zero to this bit has no effect. Writing a one to this bit will clear the corresponding bit in IMR.
AT32UC3A3 11.7.3 Name: Interrupt Mask Register IMR Access Type: Read-only Offset: 0x008 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - NMI 7 6 5 4 3 2 1 0 INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0 • INTn: External Interrupt n 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled.
AT32UC3A3 11.7.
AT32UC3A3 11.7.5 Name: Interrupt Clear Register ICR Access Type: Write-only Offset: 0x010 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - NMI 7 6 5 4 3 2 1 0 INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0 • INTn: External Interrupt n Writing a zero to this bit has no effect. Writing a one to this bit will clear the corresponding bit in ISR.
AT32UC3A3 11.7.6 Name: Mode Register MODE Access Type: Read/Write Offset: 0x014 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - NMI 7 6 5 4 3 2 1 0 INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0 • INTn: External Interrupt n 0: The external interrupt is edge triggered. 1: The external interrupt is level triggered.
AT32UC3A3 11.7.7 Name: Edge Register EDGE Access Type: Read/Write Offset: 0x018 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - NMI 7 6 5 4 3 2 1 0 INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0 • INTn: External Interrupt n 0: The external interrupt triggers on falling edge. 1: The external interrupt triggers on rising edge.
AT32UC3A3 11.7.8 Name: Level Register LEVEL Access Type: Read/Write Offset: 0x01C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - NMI 7 6 5 4 3 2 1 0 INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0 • INTn: External Interrupt n 0: The external interrupt triggers on low level. 1: The external interrupt triggers on high level.
AT32UC3A3 11.7.9 Filter Register Name: FILTER Access Type: Read/Write Offset: 0x020 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - NMI 7 6 5 4 3 2 1 0 INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0 • INTn: External Interrupt n 0: The external interrupt is not filtered. 1: The external interrupt is filtered.
AT32UC3A3 11.7.10 Test Register Name: TEST Access Type: Read/Write Offset: 0x024 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - NMI 7 6 5 4 3 2 1 0 INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0 • TESTEN: Test Enable 0: This bit disables external interrupt test mode. 1: This bit enables external interrupt test mode.
AT32UC3A3 11.7.11 Asynchronous Register Name: ASYNC Access Type: Read/Write Offset: 0x028 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - NMI 7 6 5 4 3 2 1 0 INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0 • INTn: External Interrupt n 0: The external interrupt is synchronized to CLK_SYNC. 1: The external interrupt is asynchronous.
AT32UC3A3 11.7.12 Name: Scan Register SCAN Access Type: Read/Write Offset: 0x2C Reset Value: 0x0000000 31 30 29 28 27 26 25 24 - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - 7 6 5 4 3 2 1 0 - - - - - - - EN PIN[2:0] PRESC[4:0] • EN 0: Keypad scanning is disabled 1: Keypad scanning is enabled • PRESC Prescale select for the keypad scan rate: Scan rate = 2(SCAN.
AT32UC3A3 11.7.13 Enable Register Name: EN Access Type: Write-only Offset: 0x030 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - NMI 7 6 5 4 3 2 1 0 INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0 • INTn: External Interrupt n Writing a zero to this bit has no effect. Writing a one to this bit will enable the corresponding external interrupt.
AT32UC3A3 11.7.14 Disable Register Name: DIS Access Type: Write-only Offset: 0x034 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - NMI 7 6 5 4 3 2 1 0 INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0 • INTn: External Interrupt n Writing a zero to this bit has no effect. Writing a one to this bit will disable the corresponding external interrupt.
AT32UC3A3 11.7.15 Control Register Name: CTRL Access Type: Read-only Offset: 0x038 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - NMI 7 6 5 4 3 2 1 0 INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0 • INTn: External Interrupt n 0: The corresponding external interrupt is disabled. 1: The corresponding external interrupt is enabled.
AT32UC3A3 11.8 Module Configuration The specific configuration for each EIC instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. Table 11-3. Module Configuration Feature EIC Number of external interrupts, including NMI 9 Table 11-4.
AT32UC3A3 12. Flash Controller (FLASHC) Rev: 2.2.1.3 12.1 Features • Controls flash block with dual read ports allowing staggered reads. • Supports 0 and 1 wait state bus access. • Allows interleaved burst reads for systems with one wait state, outputting one 32-bit word per clock cycle. • 32-bit HSB interface for reads from flash array and writes to page buffer. • 32-bit PB interface for issuing commands to and configuration of the controller.
AT32UC3A3 12.4 12.4.1 Functional description Bus interfaces The None has two bus interfaces, one High-Speed Bus (HSB) interface for reads from the flash array and writes to the page buffer, and one Peripheral Bus (PB) interface for writing commands and control to and reading status from the controller. 12.4.2 Memory organization To maximize performance for high clock-frequency systems, None interfaces to a flash block with two read ports.
AT32UC3A3 The flash controller supports flash blocks with up to 2^21 word addresses, as displayed in Figure 12-1. Reading the memory space between address pw and 2^21-1 returns an undefined result. The User page is permanently mapped to word address 2^21. Table 12-1. User page addresses Memory type Start address, byte sized Size Main array 0 pw words = 4pw bytes User 2^23 = 8388608 128 words = 512 bytes Figure 12-1.
AT32UC3A3 Figure 12-3. High Speed Mode Frequency 1 wait state 0 wait state Frequency limit for 0 wait state operation Speed mode H h ig al m or N 12.4.6 Quick Page Read A dedicated command, Quick Page Read (QPR), is provided to read all words in an addressed page. All bits in all words in this page are AND’ed together, returning a 1-bit result. This result is placed in the Quick Page Read Result (QPRR) bit in Flash Status Register (FSR).
AT32UC3A3 The page buffer is not automatically reset after a page write. The programmer should do this manually by issuing the Clear Page Buffer flash command. This can be done after a page write, or before the page buffer is loaded with data to be stored to the flash page. Example: Writing a word into word address 130 of a flash with 128 words in the page buffer. PAGEN will be updated with the value 1, and the word will be written into word 2 in the page buffer. 12.4.
AT32UC3A3 If the current command writes or erases a page in a locked region, or a page protected by the BOOTPROT fuses, the command has no effect on the flash memory; however, the LOCKE flag is set in the FSR register. This flag is automatically cleared by a read access to the FSR register. 12.5.1 Write/erase page operation Flash technology requires that an erase must be done before programming. The entire flash can be erased by an Erase All command.
AT32UC3A3 set and the command is cancelled. If the bit LOCKE has been written to 1 in FCR, the interrupt line rises. When the command is complete, the bit FRDY bit in the Flash Status Register (FSR) is set. If an interrupt has been enabled by setting the bit FRDY in FCR, the interrupt line of the flash controller is set. Two errors can be detected in the FSR register after issuing the command: • Programming Error: A bad keyword and/or an invalid command have been written in the FCMD register.
AT32UC3A3 through a dedicated Peripheral Bus address. Some of the general-purpose fuse bits are reserved for special purposes, and should not be used for other functions.: Table 12-2. General-purpose fuses with special functions GeneralPurpose fuse number Name Usage 15:0 LOCK Region lock bits. EPFL External Privileged Fetch Lock. Used to prevent the CPU from fetching instructions from external memories when in privileged mode. This bit can only be changed when the security bit is cleared.
AT32UC3A3 To erase or write a general-purpose fuse bit, the commands Write General-Purpose Fuse Bit (WGPB) and Erase General-Purpose Fuse Bit (EGPB) are provided. Writing one of these commands, together with the number of the fuse to write/erase, performs the desired operation. An entire General-Purpose Fuse byte can be written at a time by using the Program GP Fuse Byte (PGPFB) instruction. A PGPFB to GP fuse byte 2 is not allowed if the flash is locked by the security bit.
AT32UC3A3 12.8 User interface 12.8.1 Address map The following addresses are used by the None. All offsets are relative to the base address allocated to the flash controller. Table 12-4.
AT32UC3A3 12.8.2 Flash Control Register Name: FCR Access Type: Read/Write Offset: 0x00 Reset value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - FWS - - PROGE LOCKE - FRDY • FRDY: Flash Ready Interrupt Enable 0: Flash Ready does not generate an interrupt. 1: Flash Ready generates an interrupt.
AT32UC3A3 12.8.3 Flash Command Register Name: FCMD Access Type: Read/Write Offset: 0x04 Reset value: 0x00000000 The FCMD can not be written if the flash is in the process of performing a flash command. Doing so will cause the FCR write to be ignored, and the PROGE bit to be set. 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 KEY 23 22 21 20 PAGEN [15:8] 15 14 13 12 PAGEN [7:0] 7 6 - - 5 4 CMD • CMD: Command This field defines the flash command.
AT32UC3A3 Table 12-5. Set of commands Command Value Mnemonic Quick Page Read User Page 15 QPRUP Read High Speed Enable 16 HSEN Read High Speed Disable 17 HSDIS • PAGEN: Page number The PAGEN field is used to address a page or fuse bit for certain operations. In order to simplify programming, the PAGEN field is automatically updated every time the page buffer is written to. For every page buffer write, the PAGEN field is updated with the page number of the address being written to.
AT32UC3A3 12.8.
AT32UC3A3 • FSZ: Flash Size The size of the flash. Not all device families will provide all flash sizes indicated in the table. Table 12-7. Flash size FSZ Flash Size 0 32 KByte 1 64 kByte 2 128 kByte 3 256 kByte 4 384 kByte 5 512 kByte 6 768 kByte 7 1024 kByte • LOCKx: Lock Region x Lock Status 0: The corresponding lock region is not locked. 1: The corresponding lock region is locked.
AT32UC3A3 12.8.
AT32UC3A3 12.8.
AT32UC3A3 12.9 Fuses Settings The flash block contains 32 general purpose fuses. These 32 fuses can be found in the Flash General Purpose Fuse Register Low (FGPFRLO) of the Flash Controller (FLASHC). Some of the FGPFRLO fuses have defined meanings outside the FLASHC and are described in this section. The general purpose fuses are set by a JTAG chip erase. 12.9.1 Flash General Purpose Fuse Register Low (FGPFRLO) Table 12-8.
AT32UC3A3 • GPF30 reserved for future use • GPF29 reserved for future use • BODEN fuses set to 0b11. BOD is disabled. • BODHYST fuse set to 0b1. The BOD hystersis is enabled. • BODLEVEL fuses set to 0b111111. This is the minimum voltage trigger level. BOD will never trigger as this level is below the POR level. • BOOTPROT fuses set to 0b011. The bootloader protected size is 8KBytes. • EPFL fuse set to 0b1. External privileged fetch is not locked. • LOCK fuses set to 0b1111111111111111. No region locked.
AT32UC3A3 13. HSB Bus Matrix (HMATRIX) Rev: 2.3.0.2 13.1 Features • • • • • • • • • • 13.
AT32UC3A3 At the end of the current access, if no other request is pending, the slave remains connected to its associated default master. A slave can be associated with three kinds of default masters: no default master, last access master and fixed default master. 13.4.1.1 No Default Master At the end of the current access, if no other request is pending, the slave is disconnected from all masters. No Default Master suits low-power mode. 13.4.1.
AT32UC3A3 3. End of Burst Cycles: When the current cycle is the last cycle of a burst transfer. For defined length burst, predicted end of burst matches the size of the transfer but is managed differently for undefined length burst. 4. Slot Cycle Limit: When the slot cycle counter has reached the limit value indicating that the current master access is too long and must be broken.
AT32UC3A3 the current access, if no other request is pending, the slave is disconnected from all masters. This configuration incurs one latency cycle for the first access of a burst. Arbitration without default master can be used for masters that perform significant bursts. • Round-Robin Arbitration with Last Default Master This is a biased round-robin algorithm used by Bus Matrix arbiters. It allows the Bus Matrix to remove the one latency cycle for the last master that accessed the slave.
AT32UC3A3 13.5 User Interface Table 13-1.
AT32UC3A3 Table 13-1.
AT32UC3A3 Table 13-1.
AT32UC3A3 13.5.1 Name: Master Configuration Registers MCFG0...
AT32UC3A3 13.5.2 Name: Slave Configuration Registers SCFG0...
AT32UC3A3 13.5.3 Name: Priority Registers A For Slaves PRAS0...PRAS15 Access Type: Read/Write Offset: - Reset Value: 0x00000000 31 30 – – 23 22 – – 15 14 – – 7 6 – – 29 28 M7PR 21 20 M5PR 13 12 M3PR 5 4 M1PR 27 26 – – 19 18 – – 11 10 – – 3 2 – – 25 24 M6PR 17 16 M4PR 9 8 M2PR 1 0 M0PR • MxPR: Master x Priority Fixed priority of Master x for accessing the selected slave. The higher the number, the higher the priority.
AT32UC3A3 13.5.4 Name: Priority Registers B For Slaves PRBS0...PRBS15 Access Type: Read/Write Offset: - Reset Value: 0x00000000 31 30 – – 23 22 – – 15 14 – – 7 6 – – 29 28 M15PR 21 20 M13PR 13 12 M11PR 5 4 M9PR 27 26 – – 19 18 – – 11 10 – – 3 2 – – 25 24 M14PR 17 16 M12PR 9 8 M10PR 1 0 M8PR • MxPR: Master x Priority Fixed priority of Master x for accessing the selected slave. The higher the number, the higher the priority.
AT32UC3A3 13.5.5 Name: Special Function Registers SFR0...SFR15 Access Type: Read/Write Offset: 0x110 - 0x115 Reset Value: - 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 SFR 23 22 21 20 SFR 15 14 13 12 SFR 7 6 5 4 SFR • SFR: Special Function Register Fields Those registers are not a HMATRIX specific register. The field of those will be defined where they are used.
AT32UC3A3 13.6 Bus Matrix Connections Accesses to unused areas returns an error result to the master requesting such an access. The bus matrix has the several masters and slaves. Each master has its own bus and its own decoder, thus allowing a different memory mapping per master. The master number in the table below can be used to index the HMATRIX control registers. For example, HMATRIX MCFG0 register is associated with the CPU Data master interface. Table 13-2.
AT32UC3A3 Figure 13-1.
AT32UC3A3 14. External Bus Interface (EBI) Rev.: 1.7.0.1 14.
AT32UC3A3 14.3 Block Diagram Figure 14-1.
AT32UC3A3 14.4 I/O Lines Description Table 14-1.
AT32UC3A3 Pin Name ADDR[17] Alternate Name Pin Description BA1 ADDR[17] SDRAMC Bank 1 SMCAddress Bus Line 17 Type Active Level Output SMC/CompactFlash shared lines NRD NRD CFNOE SMC Read Signal CompactFlash CFNOE Output Low NWE0 NWE0-NWE CFNWE SMC Write Enable10 or Write enable CompactFlash CFNWE Output Low NCS[4] NCS[4] CFCS[0] SMC Chip Select Line 4 CompactFlash Chip Select Line 0 Output Low NCS[5] NCS[5] CFCS[1] SMC Chip Select Line 5 CompactFlash Chip Select Line 1 Output Low
AT32UC3A3 • CLK_ECCHRS Refer to Table 14-2 on page 167 to configure those clocks. Table 14-2. EBI Clocks Configuration Type of the Interfaced Device Clocks type SDRAM SRAM, PROM, EPROM, EEPROM, Flash NandFlash SmartMedia CompactFlash CLK_EBI HSB X X X X CLK_SDRAMC PB X CLK_SMC PB X X X CLK_ECCHRS PB Clocks name 14.5.
AT32UC3A3 Table 14-3. SFR6 Bit Number EBI Special Function Register Fields Description Bit name Description 0 = Chip Select 2 (NCS[2]) is connected to a Static Memory device. For each access to the NCS[2] memory space, all related pins act as SMC pins 2 1 0 14.6 CS2A CS1A 1 = Chip Select 2 (NCS[2]) is connected to a NandFlash or a SmartMedia device.
AT32UC3A3 14.6.5 CompactFlash Support The External Bus Interface integrates circuitry that interfaces to CompactFlash devices. The CompactFlash logic is driven by the SMC on the NCS[4] and/or NCS[5] address space. Writing to the HMATRIX.SFR6.CS4A and/or HMATRIX.SFR6.CS5A bits the appropriate value enables this logic. Access to an external CompactFlash device is then made by accessing the address space reserved to NCS[4] and/or NCS[5].
AT32UC3A3 ured to drive 8-bit memory devices on the corresponding NCS pin (NCS[4] or NCS[5]). The Data Bus Width (DBW) field in the SMC Mode (MODE) register of the NCS[4] and/or NCS[5] address space must be written as shown in Table 14-5 on page 170 to enable the required access type. NBS1 and NBS0 are the byte selection signals from SMC and are available when the SMC is set in Byte Select mode on the corresponding Chip Select. The CFCE1 and CFCE2 waveforms are identical to the corresponding NCSx waveform.
AT32UC3A3 Figure 14-3. CompactFlash Read/Write Control Signals EBI SMC Compact Flash Logic A23 1 1 0 1 0 1 A22 NRD NWR0/NWE Table 14-6. 14.6.5.
AT32UC3A3 Table 14-8. Shared CompactFlash Interface Multiplexing Access to CompactFlash Device 14.6.5.5 Pins CompactFlash Signals NRD CFNOE NWE0 CFNWE NWE1 CFNIORD CFRNW CFRNW Application example Figure 14-4 on page 172 illustrates an example of a CompactFlash application. CFCS0 and CFRNW signals are not directly connected to the CompactFlash slot 0, but do control the direction and the output enable of the buffers between the EBI and the CompactFlash Device.
AT32UC3A3 Figure 14-5. CompactFlash Application Example without I/O mode CompactFlash Connector EBI D[15:0] DATA[15:0] DIR /OE CFRNW NCS[4] _CD1 Pxx _CD2 /OE ADDR[10:0] ADDR[22] _REG NRD _OE NWE0 _WE NWE1 _IORD ADDR[21] 14.6.6 A[10:0] _IOWR CFCE1 _CE1 CFCE2 _CE2 NWAIT _WAIT SmartMedia and NAND Flash Support The EBI integrates circuitry that interfaces to SmartMedia and NAND Flash devices.
AT32UC3A3 Figure 14-6. NAND Flash Signal Multiplexing on EBI Pins EBI NandFlash Logic SMC NCS[2]/[3] NRD NANDOE NANDWE NWR0_NWE 14.6.6.1 NAND Flash signals The address latch enable and command latch enable signals on the NAND Flash device are driven by address bits ADDR[22] and ADDR[21] of the EBI address bus. The user should note that any bit on the EBI address bus can also be used for this purpose.
AT32UC3A3 14.7 14.7.1 Application Example Hardware Interface Table 14-9.
AT32UC3A3 Table 14-10.
AT32UC3A3 14.7.2 Connection Examples Figure 14-8 on page 177shows an example of connections between the EBI and external devices. Figure 14-8.
AT32UC3A3 15. Static Memory Controller (SMC) Rev. 1.0.6.5 15.1 Features • • • • • • • • • • • • 15.
AT32UC3A3 15.3 Block Diagram Figure 15-1. SMC Block Diagram (AD_MSB=23) NCS[5:0] HMatrix NCS[5:0] NRD SMC Chip Select NRD NWR0/NWE NWE0 A0/NBS0 ADDR[0] NWR1/NBS1 SMC Power Manager A1/NWR2/NBS2 CLK_SMC NWE1 EBI Mux Logic A[AD_MSB:2] D[15:0] NWAIT I/O Controller ADDR[1] ADDR[AD_MSB:2] DATA[15:0] NWAIT User Interface Peripheral Bus 15.4 I/O Lines Description Table 15-1. 15.
AT32UC3A3 15.5.1 I/O Lines The SMC signals pass through the External Bus Interface (EBI) module where they are multiplexed. The user must first configure the I/O Controller to assign the EBI pins corresponding to SMC signals to their peripheral function. If the I/O lines of the EBI corresponding to SMC signals are not used by the application, they can be used for other purposes by the I/O Controller. 15.5.2 Clocks The clock for the SMC bus interface (CLK_SMC) is generated by the Power Manager.
AT32UC3A3 Figure 15-3. Memory Connections for Six External Devices NCS[0] - NCS[5] NRD SMC NWE NCS5 A[AD_MSB:0] NCS4 D[15:0] NCS3 NCS2 NCS1 NCS0 Memory Enable Memory Enable Memory Enable Memory Enable Memory Enable Memory Enable Output Enable Write Enable 8 or 16 15.6.3 15.6.3.1 A[AD_MSB:0] D[15:0] or D[7:0] Connection to External Devices Data bus width A data bus width of 8 or 16 bits can be selected for each chip select.
AT32UC3A3 Figure 15-5. Memory Connection for a 16-bit Data Bus D[15:0] D[15:0] A[19:2] A[18:1] A1 SMC A[0] NBS0 Low Byte Enable NBS1 High Byte Enable NWE Write Enable NRD Output Enable NCS[2] Memory Enable •Byte write access The byte write access mode supports one byte write signal per byte of the data bus and a single read signal. Note that the SMC does not allow boot in byte write access mode.
AT32UC3A3 Figure 15-6. Connection of two 8-bit Devices on a 16-bit Bus: Byte Write Option D[7:0] D[7:0] D[15:8] A[24:2] SMC A[23:1] A[0] A1 NWR0 Write Enable NWR1 NRD Read Enable Memory Enable NCS[3] D[15:8] A[23:1] A[0] Write Enable Read Enable Memory Enable •Signal multiplexing Depending on the MODE.BAT bit, only the write signals or the byte select signals are used. To save I/Os at the external bus interface, control signals at the SMC interface are multiplexed.
AT32UC3A3 access type. NWR0 to NWR1 have the same timings and protocol as NWE. In the same way, NCS represents one of the NCS[0..5] chip select lines. 15.6.4.1 Read waveforms The read cycle is shown on Figure 15-7 on page 184. The read cycle starts with the address setting on the memory address bus, i.e.: {A[23:2], A1, A0} for 8-bit devices {A[23:2], A1} for 16-bit devices Figure 15-7.
AT32UC3A3 1. NCSRDSETUP: the NCS setup time is defined as the setup time of address before the NCS falling edge. 2. NCSRDPULSE: the NCS pulse length is the time between NCS falling edge and NCS rising edge. 3. NCSRDHOLD: the NCS hold time is defined as the hold time of address after the NCS rising edge. •Read cycle The NRDCYCLE time is defined as the total duration of the read cycle, i.e., from the time where address is set on the address bus to the point where address may change.
AT32UC3A3 Figure 15-8. No Setup, No Hold on NRD, and NCS Read Signals CLK_SMC A[AD_MSB:2] NBS0, NBS1, A0, A1 NRD NCS D[15:0] NRDSETUP NRDPULSE NRDPULSE NCSRDPULSE NCSRDPULSE NCSRDPULSE NRDCYCLE NRDCYCLE NRDCYCLE • Null Pulse Programming null pulse is not permitted. Pulse must be at least written to one. A null value leads to unpredictable behavior. 15.6.4.
AT32UC3A3 Figure 15-9. READMODE = 1: Data Is Sampled by SMC Before the Rising Edge of NRD CLK_SMC A[AD_MSB:2] NBS0, NBS1, A0, A1 NRD NCS tPACC D[15:0] Data Sampling •Read is controlled by NCS (MODE.READMODE = 0) Figure 15-10 on page 188 shows the typical read cycle of an LCD module. The read data is valid tPACC after the falling edge of the NCS signal and remains valid until the rising edge of NCS. Data must be sampled when NCS is raised. In that case, the MODE.
AT32UC3A3 Figure 15-10. READMODE = 0: Data Is Sampled by SMC Before the Rising Edge of NCS CLK_SMC A[AD_MSB:2] NBS0, NBS1, A0, A1 NRD NCS tPACC D[15:0] Data Sampling 15.6.4.3 Write waveforms The write protocol is similar to the read protocol. It is depicted in Figure 15-11 on page 189. The write cycle starts with the address setting on the memory address bus. •NWE waveforms The NWE signal is characterized by a setup timing, a pulse width and a hold timing. 1.
AT32UC3A3 Figure 15-11. Write Cycle CLK_SMC A[AD_MSB:2] NBS0, NBS1, A0, A1 NWE NCS NWESETUP NCSWRSETUP NWEPULSE NCSWRPULSE NWEHOLD NCSWRHOLD NWECYCLE •Write cycle The write cycle time is defined as the total duration of the write cycle, that is, from the time where address is set on the address bus to the point where address may change.
AT32UC3A3 •Null delay setup and hold If null setup parameters are programmed for NWE and/or NCS, NWE and/or NCS remain active continuously in case of consecutive write cycles in the same memory (see Figure 15-12 on page 190). However, for devices that perform write operations on the rising edge of NWE or NCS, such as SRAM, either a setup or a hold must be programmed. Figure 15-12.
AT32UC3A3 Figure 15-13. WRITEMODE = 1. The Write Operation Is Controlled by NWE CLK_SMC A[AD_MSB:2] NBS0, NBS1, A0, A1 NWE, NWR0, NWR1 NCS D[15:0] •Write is controlled by NCS (MODE.WRITEMODE = 0) Figure 15-14 on page 191 shows the waveforms of a write operation with MODE.WRITEMODE written to zero. The data is put on the bus during the pulse and hold steps of the NCS signal.
AT32UC3A3 15.6.4.6 Coding timing parameters All timing parameters are defined for one chip select and are grouped together in one register according to their type. The Setup register (SETUP) groups the definition of all setup parameters: • NRDSETUP, NCSRDSETUP, NWESETUP, and NCSWRSETUP. The Pulse register (PULSE) groups the definition of all pulse parameters: • NRDPULSE, NCSRDPULSE, NWEPULSE, and NCSWRPULSE. The Cycle register (CYCLE) groups the definition of all cycle parameters: • NRDCYCLE, NWECYCLE.
AT32UC3A3 15.6.5 15.6.5.1 Automatic Wait States Under certain circumstances, the SMC automatically inserts idle cycles between accesses to avoid bus contention or operation conflict. Chip select wait states The SMC always inserts an idle cycle between two transfers on separate chip selects. This idle cycle ensures that there is no bus contention between the deactivation of one device and the activation of the next one.
AT32UC3A3 An early read wait state is automatically inserted if at least one of the following conditions is valid: • if the write controlling signal has no hold time and the read controlling signal has no setup time (Figure 15-16 on page 194). • in NCS write controlled mode (MODE.WRITEMODE = 0), if there is no hold timing on the NCS signal and the NCSRDSETUP parameter is set to zero, regardless of the read mode (Figure 15-17 on page 195). The write operation must end with a NCS rising edge.
AT32UC3A3 Figure 15-17. Early Read Wait State: NCS Controlled Write with No Hold Followed by a Read with No Setup.
AT32UC3A3 Figure 15-18. Early Read Wait State: NWE-controlled Write with No Hold Followed by a Read with one Set-up Cycle. CLK_SMC A[AD_MSB:2] NBS0, NBS1, A0, A1 Internal write controlling signal external write controlling signal(NWE) No hold Read setup=1 NRD D[15:0] Write cycle (WRITEMODE = 1) 15.6.5.3 Early Read Wait State Read cycle (READMODE=0 or READMODE=1) Reload user configuration wait state The user may change any of the configuration parameters by writing the SMC user interface.
AT32UC3A3 •Slow clock mode transition A reload configuration wait state is also inserted when the slow clock mode is entered or exited, after the end of the current transfer (see Section 15.6.8). 15.6.5.4 Read to write wait state Due to an internal mechanism, a wait cycle is always inserted between consecutive read and write SMC accesses. This wait cycle is referred to as a read to write wait state in this document.
AT32UC3A3 Figure 15-19. TDF Period in NRD Controlled Read Access (TDFCYCLES = 2) CLK_SMC A[AD_MSB:2] NBS0, NBS1, A0, A1 NRD NCS D[15:0] tPACC TDF = 2 clock cycles NRD controlled read operation Figure 15-20.
AT32UC3A3 15.6.6.2 TDF optimization enabled (MODE.TDFMODE = 1) When the MODE.TDFMODE bit is written to one (TDF optimization is enabled), the SMC takes advantage of the setup period of the next access to optimize the number of wait states cycle to insert. Figure 15-21 on page 199 shows a read access controlled by NRD, followed by a write access controlled by NWE, on Chip Select 0.
AT32UC3A3 • read access followed by a write access on the same chip select. with no TDF optimization. Figure 15-22. TDF Optimization Disabled (MODE.TDFMODE = 0). TDF Wait States between Two Read Accesses on Different Chip Selects.
AT32UC3A3 Figure 15-24. TDF Optimization Disabled (MODE.TDFMODE = 0). TDF Wait States between Read and Write accesses on the Same Chip Select. CLK_SMC A[AD_MSB:2] NBS0, NBS1, A0, A1 Read1 controlling signal(NRD) Write2 setup = 1 Read1 hold = 1 Write2 controlling signal(NWE) TDFCYCLES = 5 D[15:0] 4 TDF WAIT STATES Read1 cycle TDFCYCLES = 5 15.6.
AT32UC3A3 The assertion of the NWAIT signal outside the expected period is ignored as illustrated in Figure 15-26 on page 203. Figure 15-25. Write Access with NWAIT Assertion in Frozen Mode (MODE.EXNWMODE = 2).
AT32UC3A3 Figure 15-26. Read Access with NWAIT Assertion in Frozen Mode (MODE.EXNWMODE = 2).
AT32UC3A3 15.6.7.3 Ready mode In Ready mode (MODE.EXNWMODE = 3), the SMC behaves differently. Normally, the SMC begins the access by down counting the setup and pulse counters of the read/write controlling signal. In the last cycle of the pulse phase, the resynchronized NWAIT signal is examined. If asserted, the SMC suspends the access as shown in Figure 15-27 on page 204 and Figure 15-28 on page 205. After deassertion, the access is completed: the hold step of the access is performed.
AT32UC3A3 Figure 15-28. NWAIT Assertion in Read Access: Ready Mode (EXNWMODE = 3).
AT32UC3A3 15.6.7.4 NWAIT latency and read/write timings There may be a latency between the assertion of the read/write controlling signal and the assertion of the NWAIT signal by the device. The programmed pulse length of the read/write controlling signal must be at least equal to this latency plus the two cycles of resynchronization plus one cycle. Otherwise, the SMC may enter the hold state of the access without detecting the NWAIT signal assertion. This is true in frozen mode as well as in ready mode.
AT32UC3A3 15.6.8 Slow Clock Mode The SMC is able to automatically apply a set of “slow clock mode” read/write waveforms when an internal signal driven by the SMC’s Power Management Controller is asserted because CLK_SMC has been turned to a very slow clock rate (typically 32 kHz clock rate). In this mode, the user-programmed waveforms are ignored and the slow clock mode waveforms are applied.
AT32UC3A3 15.6.8.2 Switching from (to) slow clock mode to (from) normal mode When switching from slow clock mode to the normal mode, the current slow clock mode transfer is completed at high clock rate, with the set of slow clock mode parameters. See Figure 15-31 on page 208. The external device may not be fast enough to support such timings. Figure 15-32 on page 209 illustrates the recommended procedure to properly switch from one mode to the other. Figure 15-31.
AT32UC3A3 Figure 15-32. Recommended Procedure to Switch from Slow Clock Mode to Normal Mode or from Normal Mode to Slow Clock Mode Slow Clock Mode Internal signal from PM CLK_SMC A[AD_MSB:2] NBS0, NBS1, A0, A1 NWE 1 1 1 2 3 2 NCS SLOW CLOCK MODE WRITE IDLE STATE NORMAL MODE WRITE Reload Configuration Wait State 15.6.9 Asynchronous Page Mode The SMC supports asynchronous burst reads in page mode, providing that the Page Mode Enabled bit is written to one in the MODE register (MODE.PMEN).
AT32UC3A3 Figure 15-33. Page Mode Read Protocol (Address MSB and LSB Are Defined in Table 15-6 on page 209) CLK_SMC A[MSB] A[LSB] NRD tpa tsa NCS tsa D[15:0] NCSRDPULSE NRDPULSE NRDPULSE The NRD and NCS signals are held low during all read transfers, whatever the programmed values of the setup and hold timings in the User Interface may be. Moreover, the NRD and NCS timings are identical. The pulse length of the first access to the page is defined with the PULSE.NCSRDPULSE field value.
AT32UC3A3 15.6.9.3 Page mode restriction The page mode is not compatible with the use of the NWAIT signal. Using the page mode and the NWAIT signal may lead to unpredictable behavior. 15.6.9.4 Sequential and non-sequential accesses If the chip select and the MSB of addresses as defined in Table 15-6 on page 209 are identical, then the current access lies in the same page as the previous one, and no page break occurs.
AT32UC3A3 15.7 User Interface The SMC is programmed using the registers listed in Table 15-8 on page 212. For each chip select, a set of four registers is used to program the parameters of the external device connected on it. In Table 15-8 on page 212, “CS_number” denotes the chip select number. Sixteen bytes (0x10) are required per chip select. The user must complete writing the configuration by writing anyone of the Mode Registers. Table 15-8.
AT32UC3A3 15.7.
AT32UC3A3 15.7.
AT32UC3A3 15.7.3 Cycle Register Register Name: CYCLE Access Type: Read/Write Offset: 0x08 + CS_number*0x10 Reset Value: 0x00030003 31 30 29 28 27 26 25 24 – – – – – – – NRDCYCLE[8] 23 22 21 20 19 18 17 16 NRDCYCLE[7:0] 15 14 13 12 11 10 9 8 – – – – – – – NWECYCLE[8] 7 6 5 4 3 2 1 0 NWECYCLE[7:0] • NRDCYCLE[8:0]: Total Read Cycle Length The total read cycle length is the total duration in clock cycles of the read cycle.
AT32UC3A3 15.7.4 Mode Register Register Name: MODE Access Type: Read/Write Offset: 0x0C + CS_number*0x10 Reset Value: 0x10002103 31 30 29 28 – – 23 22 21 20 – – – TDFMODE 15 14 13 12 – – 7 6 – – PS DBW 5 4 EXNWMODE 27 26 25 24 – – – PMEN 19 18 17 16 TDFCYCLES 11 10 9 8 – – – BAT 3 2 1 0 – – WRITEMODE READMODE • PS: Page Size If page mode is enabled, this field indicates the size of the page in bytes.
AT32UC3A3 • DBW: Data Bus Width DBW Data Bus Width 0 8-bit bus 1 16-bit bus 2 Reserved 3 Reserved • BAT: Byte Access Type This field is used only if DBW defines a 16-bit data bus.
AT32UC3A3 • READMODE: Read Mode READMODE Read Access Mode 0 The read operation is controlled by the NCS signal. If TDF are programmed, the external bus is marked busy after the rising edge of NCS. If TDF optimization is enabled (TDFMODE = 1), TDF wait states are inserted after the setup of NCS. 1 The read operation is controlled by the NRD signal. If TDF cycles are programmed, the external bus is marked busy after the rising edge of NRD.
AT32UC3A3 16. SDRAM Controller (SDRAMC) Rev: 2.2.0.4 16.1 Features • 128-Mbytes address space • Numerous configurations supported • • • • • • 16.
AT32UC3A3 16.3 Block Diagram Figure 16-1.
AT32UC3A3 Table 16-1. 16.5 16.5.1 I/O Lines Description Name Description Type Active Level DQM[1:0] Data Mask Enable Signals Output High SDRAMC_A[12:0] Address Bus Output D[15:0] Data Bus Input/Output Application Example Hardware Interface Figure 16-2 on page 221 shows an example of SDRAM device connection using a 16-bit data bus width.
AT32UC3A3 16.5.2.1 16-bit memory data bus width Table 16-2. SDRAM Configuration Mapping: 2K Rows, 256/512/1024/2048 Columns CPU Address Line 27 26 25 24 23 22 21 20 19 18 17 16 15 BA[1:0] 13 12 11 10 9 8 7 6 Row[10:0] BA[1:0] BA[1:0] 5 4 3 2 1 Column[7:0] Row[10:0] M0 Column[9:0] Row[10:0] 0 M0 Column[8:0] Row[10:0] BA[1:0] Table 16-3.
AT32UC3A3 16.6.3 Clocks The clock for the SDRAMC bus interface (CLK_SDRAMC) is generated by the Power Manager. This clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the SDRAMC before disabling the clock, to avoid freezing the SDRAMC in an undefined state. 16.6.4 Interrupts The SDRAMC interrupt request line is connected to the interrupt controller. Using the SDRAMC interrupt requires the interrupt controller to be programmed first. 16.7 16.7.
AT32UC3A3 quency, the TR register must be written with the value 1562 (15.625 µs x 100 MHz) or 781 (7.81 µs x 100 MHz). After initialization, the SDRAM devices are fully functional. Figure 16-3. SDRAM Device Initialization Sequence SDCKE tRP tRC tMRD SDCK SDRAMC_A[9:0] A10 SDRAMC_A[12:11] SDCS RAS CAS SDWE DQM Inputs Stable for 200 usec 16.7.
AT32UC3A3 Figure 16-4. Write Burst, 16-bit SDRAM Access tRCD = 3 SDCS SDCK SDRAMC_A[12:0] Row n Col a Col b Col c Col d Col e Col f Col g Col h Col i Col j Col k Col l Dnb Dnc Dnd Dne Dnf Dng Dnh Dni Dnj Dnk Dnl RAS CAS SDWE D[15:0] 16.7.3 Dna SDRAM Controller Read Cycle The SDRAMC allows burst access, incremental burst of unspecified length or single access. In all cases, the SDRAMC keeps track of the active row in each bank, thus maximizing performance of the SDRAM.
AT32UC3A3 Figure 16-5. Read Burst, 16-bit SDRAM Access tRCD = 3 CAS = 2 SDCS SDCK SDRAMC_A[12:0] Row n Col a Col b Col c Col d Col e Col f RAS CAS SDWE D[15:0] (Input) 16.7.4 Dna Dnb Dnc Dnd Dne Dnf Border Management When the memory row boundary has been reached, an automatic page break is inserted. In this case, the SDRAMC generates a precharge command, activates the new row and initiates a read or write command.
AT32UC3A3 Figure 16-6. Read Burst with Boundary Row Access TRP = 3 CAS = 2 TRCD = 3 SDCS SDCK Row n SDRAMC_A[12:0] Col a Col b Col c Col d Row m Col a Col b Col c Col d Col e RAS CAS SDWE D[15:0] 16.7.5 Dna Dnb Dnc Dnd Dma Dmb Dmc Dmd Dme SDRAM Controller Refresh Cycles An auto refresh command is used to refresh the SDRAM device. Refresh addresses are generated internally by the SDRAM device and incremented after each auto refresh automatically.
AT32UC3A3 Figure 16-7. Refresh Cycle Followed by a Read Access tRP = 3 tRC = 8 tRCD = 3 CAS = 2 SDCS SDCK Row n SDRAMC_A[12:0] Col c Col d Row m Col a RAS CAS SDWE D[15:0] (input) 16.7.6 Dnb Dnc Dnd Dma Power Management Three low power modes are available: • Self refresh mode: the SDRAM executes its own auto refresh cycles without control of the SDRAMC. Current drained by the SDRAM is very low. • Power-down mode: auto refresh cycles are controlled by the SDRAMC.
AT32UC3A3 and Drive Strength (DS) parameters must be set by writing the corresponding fields in the LPR register, and transmitted to the low power SDRAM device during initialization. After initialization, as soon as the LPR.PASR, LPR.DS, or LPR.TCSR fields are modified and self refresh mode is activated, the SDRAMC issues an Extended Load Mode Register command to the SDRAM and the Extended Mode Register of the SDRAM device is accessed automatically.
AT32UC3A3 Figure 16-9. Low Power Mode Behavior TRCD = 3 CAS = 2 Low Power Mode SDCS SDCK SDRAMC_A[12:0] Row n Col a Col b Col c Col d Col e Col f RAS CAS SDCKE D[15:0] (input) 16.7.6.3 Dna Dnb Dnc Dnd Dne Dnf Deep power-down mode This mode is selected by writing the value three to the LPR.LPCB field. When this mode is activated, all internal voltage generators inside the SDRAM are stopped and all data is lost.
AT32UC3A3 Figure 16-10.
AT32UC3A3 16.8 User Interface Table 16-5.
AT32UC3A3 16.8.1 Mode Register Register Name: MR Access Type: Read/Write Offset: 0x00 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - MODE • MODE: Command Mode This field defines the command issued by the SDRAMC when the SDRAM device is accessed. MODE Description 0 Normal mode.
AT32UC3A3 16.8.2 Refresh Timer Register Register Name: TR Access Type: Read/Write Offset: 0x04 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - 7 6 5 4 1 0 COUNT[11:8] 3 2 COUNT[7:0] • COUNT[11:0]: Refresh Timer Count This 12-bit field is loaded into a timer that generates the refresh pulse. Each time the refresh pulse is generated, a refresh burst is initiated.
AT32UC3A3 16.8.3 Configuration Register Register Name: CR Access Type: Read/Write Offset: 0x08 Reset Value: 0x852372C0 31 30 29 28 27 26 TXSR 23 22 21 14 20 19 18 13 DBW 6 16 12 11 10 9 8 1 0 TWR 5 CAS 17 TRP TRC 7 24 TRAS TRCD 15 25 4 NB 3 2 NR NC • TXSR: Exit Self Refresh to Active Delay Reset value is eight cycles. This field defines the delay between SCKE set high and an Activate command in number of cycles. Number of cycles is between 0 and 15.
AT32UC3A3 • CAS: CAS Latency Reset value is two cycles. In the SDRAMC, only a CAS latency of one, two and three cycles is managed. CAS CAS Latency (Cycles) 0 Reserved 1 1 2 2 3 3 • NB: Number of Banks Reset value is two banks. NB Number of Banks 0 2 1 4 • NR: Number of Row Bits Reset value is 11 row bits. NR Row Bits 0 11 1 12 2 13 3 Reserved • NC: Number of Column Bits Reset value is 8 column bits.
AT32UC3A3 16.8.4 High Speed Register Register Name: HSR Access Type: Read/Write Offset: 0x0C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - DA • DA: Decode Cycle Enable A decode cycle can be added on the addresses as soon as a non-sequential access is performed on the HSB bus.
AT32UC3A3 16.8.
AT32UC3A3 • LPCB: Low Power Configuration Bits LPCB Low Power Configuration 0 Low power feature is inhibited: no power-down, self refresh or deep power-down command is issued to the SDRAM device. 1 The SDRAMC issues a self refresh command to the SDRAM device, the SDCLK clock is deactivated and the SDCKE signal is set low. The SDRAM device leaves the self refresh mode when accessed and enters it after the access.
AT32UC3A3 16.8.6 Interrupt Enable Register Register Name: IER Access Type: Write-only Offset: 0x14 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - RES Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR.
AT32UC3A3 16.8.7 Interrupt Disable Register Register Name: IDR Access Type: Write-only Offset: 0x18 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - RES Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR.
AT32UC3A3 16.8.8 Interrupt Mask Register Register Name: IMR Access Type: Read-only Offset: 0x1C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - RES 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled.
AT32UC3A3 16.8.9 Interrupt Status Register Register Name: ISR Access Type: Read-only Offset: 0x20 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - RES • RES: Refresh Error Status This bit is set when a refresh error is detected. This bit is cleared when the register is read.
AT32UC3A3 16.8.
AT32UC3A3 16.8.11 Version Register Register Name: VERSION Access Type: Read-only Offset: 0xFC Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 1 0 VARIANT 11 10 VERSION 3 2 VERSION • Variant: Variant Number Reserved. No functionality associated. • Version: Version Number Version number of the module.No functionality associated.
AT32UC3A3 17. Error Corrected Code Controller (ECCHRS) Rev. 1.0.0.0 17.1 Features • Hardware Error Corrected Code Generation with two methods : • • • • 17.
AT32UC3A3 17.3 Block Diagram Figure 17-1. ECCHRS Block Diagram NAND Flash SmartMedia Logic Encoder RS4 Rom 1024x10 Partial Syndrome Static Memory Controller 10 GF(2 ) Polynomial process Error Evaluator Chien Search ECC Controller Ctrl/ECC 1bit Algorithm HECC User Interface Peripheral Bus 17.4 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 17.4.
AT32UC3A3 17.5 Functional Description A page in NAND Flash and SmartMedia™ memories contains an area for main data and an additional area used for redundancy (ECC). The page is organized in 8-bit or 16-bit words. The page size corresponds to the number of words in the main area plus the number of words in the extra area used for redundancy. Over time, some memory locations may fail to program or erase properly.
AT32UC3A3 Figure 17-2. FREEZE signal waveform Spare Zone Nand Flash page 2048B 512B 512B 512B 512B FREEZE The application can check the ECC Status Registers (SR1/SR2) for any detected errors. It is up to the application to correct any detected error for ECC-H. The application can correct any detected error or let the hardware do the correction by writing a one to the Correction Enable bit in the MD register (MD.CORRS4) for ECC-RS.
AT32UC3A3 Figure 17-3.
AT32UC3A3 Figure 17-4.
AT32UC3A3 For ECC-RS, in order to perform 4-error correction per 512 bytes of 8-bit words, the codeword have to be generated by the RS4 Encoder module and stored into the NAND Flash extra area, according to the scheme shown in Figure 17-5 on page 252 Figure 17-5. RS Codeword Generation Feedback α28 α 500 CW7 + α 397 CW6 + α 402 CW5 + α 603 CW4 + α 395 CW3 + α 383 CW2 + α 539 CW1 + + DataIn CW0 In read mode, firstly, the detection for any error is done with the partial syndrome module.
AT32UC3A3 Figure 17-7. Error Evaluator Block Diagram ω0 α -1 α -3 α -4 α-5 α -7 ω1 ω3 ω4 ω5 ω7 + ω (α ) -j Λ odd( α ) -j Rom 1024x10 10 GF(2 ) inverted Error value @ position j Array - Mult ErrorLoc The Chien Search takes charge of determining if an error has occurred at symbol N according to the scheme in Figure 17-8 on page 253 Figure 17-8.
AT32UC3A3 17.6 User Interface Table 17-1.
AT32UC3A3 17.6.1 Name: Control Register CR Access Type: Write-only Offset: 0x000 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - RST • RST: RESET Parity Writing a one to this bit will reset the ECC Parity registers. Writing a zero to this bit has no effect. This bit always reads as zero.
AT32UC3A3 17.6.2 Name: Mode Register MD Access Type: Read/Write Offset: 0x004 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - CORRS4 - FREEZE 7 6 5 4 3 2 1 0 - TYPECORREC - PAGESIZE • CORRS4: Correction Enable Writing a one to this bit will enable the correction to be done after the Partial Syndrome process and allow interrupt to be sent to CPU.
AT32UC3A3 • PAGESIZE: Page Size This table defines the page size of the NAND Flash device when using the ECC-H code (TYPECORREC = 0b0xx). Page Size Description 0 528 words 1 1056 words 2 2112 words 3 4224 words Others Reserved A word has a value of 8 bits or 16 bits, depending on the NAND Flash or SmartMedia™ memory organization.
AT32UC3A3 17.6.3 Name: Status Register 1 SR1 Access Type: Read-only Offset: 0x008 Reset Value: 0x000000000 MD.
AT32UC3A3 • RECERRn: Recoverable Error in the packet number n of 256/512 Bytes in the page 1: Errors detected. If MULERRn is zero, a single correctable error was detected. Otherwise multiple uncorrected errors were detected. 0: No errors have been detected. TYPECORREC sector size Comments 0 page size 1 256 RECERR0 to RECERR7 are used depending on the page size 2 512 RECERR0 to RECERR7 are used depending on the page size Others Reserved Only RECERR0 is used MD.
AT32UC3A3 Bit Index (n) Sector Boundaries 5 2560-3071 6 3072-3583 7 3584-4095 260 32072H–AVR32–10/2012
AT32UC3A3 17.6.4 Name: Parity Register 0 PR0 Access Type: Read-only Offset: 0x00C Reset Value: 0x00000000 Using ECC-H code, one bit correction per page (MD.
AT32UC3A3 NPARITY0[3:0] 7 6 0 5 WORDADD0[4:0] 4 3 WORDADD0[7:5] 2 1 0 BITADDR0 Once the entire main area of a page is written with data, this register content must be stored at any free location of the spare area. • NPARITY0: Parity N Parity calculated by the ECC-H. • WORDADDR0: Corrupted Word Address in the page between the first byte and the 255th byte During a page read, this field contains the word address (8-bit word) where an error occurred, if a single error was detected.
AT32UC3A3 Using ECC-H code, one bit correction per sector of 512 bytes (MD.TYPECORREC=0b010) 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 10 9 8 NPARITY0[11:4] 15 14 13 12 11 NPARITY0[3:0] 7 6 WORDADD0[8:5] 5 WORDADD0[4:0] 4 3 2 1 0 BITADDR0 Once the entire main area of a page is written with data, this register content must be stored at any free location of the spare area. • NPARITY0: Parity N Parity calculated by the ECC-H.
AT32UC3A3 17.6.5 Name: Parity Register 1 PR1 Access Type: Read-only Offset: 0x010 Reset Value: 0x00000000 Using ECC-H code, one bit correction per page (MD.
AT32UC3A3 Once the entire main area of a page is written with data, this register content must be stored at any free location of the spare area. • NPARITY1: Parity N Parity alculated by the ECC-H. • WORDADDR1: corrupted Word Address in the page between the 256th and the 511th byte During a page read, this field contains the word address (8-bit word) where an error occurred, if a single error was detected. If multiple errors were detected, this field is meaningless.
AT32UC3A3 17.6.6 Name: Status Register 2 SR2 Access Type: Read-only Offset: 0x014 Reset Value: 0x00000000 MD.
AT32UC3A3 MD.TYPECORREC=0b1xx, using ECC-RS code 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - MULERR RECERR Only one sub page of 512 bytes is corrected at a time. If several sub page are on error then it is necessary to do several time the correction process.
AT32UC3A3 17.6.7 Name: Parity Register 2 - 15 PR2 - PR15 Access Type: Read-only Offset: 0x018 - 0x04C Reset Value: 0x00000000 Using ECC-H code, one bit correction per sector of 256 bytes (MD.
AT32UC3A3 Using ECC-H code, one bit correction per sector of 512 bytes (MD.TYPECORREC=0b010) 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 10 9 8 NPARITYn[11:4] 15 14 13 12 11 NPARITYn[3:0] 7 6 WORDADDn[8:5] 5 WORDADDn[4:0] 4 3 2 1 0 BITADDRn Once the entire main area of a page is written with data, this register content must be stored to any free location of the spare area. Only PR2 to PR7 registers are available in this case.
AT32UC3A3 17.6.8 Name: Codeword 00 - Codeword79 CWPS00 - CWPS79 Access Type: Read-only Offset: 0x050 - 0x18C Reset Value: 0x00000000 Page Write: 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 CODEWORD • CODEWORD: Once the 512 bytes of a page is written with data, this register content must be stored to any free location of the spare area.
AT32UC3A3 • PARSYND: At the end of a page read, this field contains the Partial Syndrome S.
AT32UC3A3 17.6.9 Name: Mask Data 0 - Mask Data 3 MDATA0 -MDATA3 Access Type: Read-only Offset: 0x190 - 0x19C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - 7 6 5 4 3 2 MASKDATA[9:8] 1 0 MASKDATA[7:0] • MASKDATA: At the end of the correction process, this field contains the mask to be XORed with the data read to perform the final correction.
AT32UC3A3 17.6.10 Name: Address Offset 0 - Address Offset 3 ADOFF0 - ADOFF3 Access Type: Read-only Offset: 0x1A0 - 0x1AC Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - 7 6 5 4 3 2 OFFSET[9:8] 1 0 OFFSET[7:0] • OFFSET: At the end of correction process, this field contains the offset address of the data read to be corrected. This field is meaningless if MD.
AT32UC3A3 17.6.11 Name: Interrupt Enable Register IER Access Type: Write-only Offset: 0x1B0 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - ENDCOR • ENDCOR: Writing a zero to this bit has no effect. Writing a one to this bit will set the corresponding bit in IMR.
AT32UC3A3 17.6.12 Name: Interrupt Disable Register IDR Access Type: Write-only Offset: 0x1B4 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - ENDCOR • ENDCOR: Writing a zero to this bit has no effect. Writing a one to this bit will clear the corresponding bit in IMR.
AT32UC3A3 17.6.13 Name: Interrupt Mask Register IMR Access Type: Read-only Offset: 0x1B8 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - ENDCOR • ENDCOR: 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. This bit is cleared when the corresponding bit in IDR is written to one.
AT32UC3A3 17.6.14 Name: Interrupt Status Register ISR Access Type: Read-only Offset: 0x1BC Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - ENDCOR • ENDCOR: This bit is cleared when the corresponding bit in ISCR is written to one. This bit is set when a correction process has ended.
AT32UC3A3 17.6.15 Name: Interrupt Status Clear Register ISCR Access Type: Write-only Offset: 0x1C0 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - ENDCOR • ENDCOR: Writing a zero to this bit has no effect Writing a one to this bit will clear the corresponding bit in ISR and the corresponding interrupt request.
AT32UC3A3 17.6.16 Name: Version Register VERSION Access Type: Read-only Offset: 0x1FC Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - 15 14 13 12 11 - - - - 7 6 5 4 VARIANT 10 9 8 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated.
AT32UC3A3 17.7 Module Configuration The specific configuration for the ECCHRS instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks according to the table in the Power Manager section. Table 17-2. Module clock name Module name Clock name ECCHRS CLK_ECCHRS Table 17-3.
AT32UC3A3 18. Peripheral DMA Controller (PDCA) Rev: 1.1.0.1 18.1 Features • • • • 18.2 Multiple channels Generates transfers between memories and peripherals such as USART and SPI Two address pointers/counters per channel allowing double buffering Performance monitors to measure average and maximum transfer latency Overview The Peripheral DMA Controller (PDCA) transfers data between on-chip peripheral modules such as USART, SPI and memories (those memories may be on- and off-chip memories).
AT32UC3A3 18.3 Block Diagram Figure 18-1. PDCA Block Diagram Peripheral 0 Memory HSB to PB Bridge HSB Peripheral Bus HSB High Speed Bus Matrix HSB Interrupt Controller IRQ Peripheral 2 ... Peripheral DMA Controller (PDCA) Peripheral 1 Peripheral (n-1) Handshake Interfaces 18.4 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 18.4.
AT32UC3A3 18.5 18.5.1 Functional Description Basic Operation The PDCA consists of multiple independent PDCA channels, each capable of handling DMA requests in parallel. Each PDCA channels contains a set of configuration registers which must be configured to start a DMA transfer. In this section the steps necessary to configure one PDCA channel is outlined. The peripheral to transfer data to or from must be configured correctly in the Peripheral Select Register (PSR).
AT32UC3A3 18.5.5 Peripheral Selection The Peripheral Select Register (PSR) decides which peripheral should be connected to the PDCA channel. A peripheral is selected by writing the corresponding Peripheral Identity (PID) to the PID field in the PSR register. Writing the PID will both select the direction of the transfer (memory to peripheral or peripheral to memory), which handshake interface to use, and the address of the peripheral holding register.
AT32UC3A3 bit in the Interrupt Status Register (ISR.TERR) will be set and the DMA channel that caused the error will be stopped. In order to restart the channel, the user must program the Memory Address Register to a valid address and then write a one to the Error Clear bit in the Control Register (CR.ECLR). If the Transfer Error interrupt is enabled, an interrupt request will be generated when a transfer error occurs. 18.
AT32UC3A3 18.7 18.7.1 User Interface Memory Map Overview Table 18-1. PDCA Register Memory Map Address Range Contents 0x000 - 0x03F DMA channel 0 configuration registers 0x040 - 0x07F DMA channel 1 configuration registers ... ... (0x000 - 0x03F)+m*0x040 DMA channel m configuration registers 0x800-0x830 Performance Monitor registers 0x834 Version register The channels are mapped as shown in Table 18-1.
AT32UC3A3 18.7.3 Performance Monitor Memory Map Table 18-3.
AT32UC3A3 18.7.5 Name: Memory Address Register MAR Access Type: Read/Write Offset: 0x000 + n*0x040 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 18 17 16 11 10 9 8 3 2 1 0 MADDR[31:24] 23 22 21 20 19 MADDR[23:16] 15 14 13 12 MADDR[15:8] 7 6 5 4 MADDR[7:0] • MADDR: Memory Address Address of memory buffer. MADDR should be programmed to point to the start of the memory buffer when configuring the PDCA.
AT32UC3A3 18.7.6 Name: Peripheral Select Register PSR Access Type: Read/Write Offset: 0x004 + n*0x040 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 PID • PID: Peripheral Identifier The Peripheral Identifier selects which peripheral should be connected to the DMA channel.
AT32UC3A3 18.7.7 Name: Transfer Counter Register TCR Access Type: Read/Write Offset: 0x008 + n*0x040 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 3 2 1 0 TCV[15:8] 7 6 5 4 TCV[7:0] • TCV: Transfer Counter Value Number of data items to be transferred by the PDCA. TCV must be programmed with the total number of transfers to be made.
AT32UC3A3 18.7.8 Name: Memory Address Reload Register MARR Access Type: Read/Write Offset: 0x00C + n*0x040 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 MARV[31:24] 23 22 21 20 MARV[23:16] 15 14 13 12 MARV[15:8] 7 6 5 4 MARV[7:0] • MARV: Memory Address Reload Value Reload Value for the MAR register. This value will be loaded into MAR when TCR reaches zero if the TCRR register has a nonzero value.
AT32UC3A3 18.7.9 Name: Transfer Counter Reload Register TCRR Access Type: Read/Write Offset: 0x010 + n*0x040 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 3 2 1 0 TCRV[15:8] 7 6 5 4 TCRV[7:0] • TCRV: Transfer Counter Reload Value Reload value for the TCR register. When TCR reaches zero, it will be reloaded with TCRV if TCRV has a positive value.
AT32UC3A3 18.7.10 Name: Control Register CR Access Type: Write-only Offset: 0x014 + n*0x040 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - ECLR 7 6 5 4 3 2 1 0 - - - - - - TDIS TEN • ECLR: Transfer Error Clear Writing a zero to this bit has no effect. Writing a one to this bit will clear the Transfer Error bit in the Status Register (SR.TERR).
AT32UC3A3 18.7.11 Name: Mode Register MR Access Type: Read/Write Offset: 0x018 + n*0x040 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - SIZE • SIZE: Size of Transfer Table 18-5.
AT32UC3A3 18.7.12 Name: Status Register SR Access Type: Read-only Offset: 0x01C + n*0x040 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - TEN • TEN: Transfer Enabled This bit is cleared when the TDIS bit in CR is written to one. This bit is set when the TEN bit in CR is written to one.
AT32UC3A3 18.7.13 Name: Interrupt Enable Register IER Access Type: Write-only Offset: 0x020 + n*0x040 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - TERR TRC RCZ Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR.
AT32UC3A3 18.7.14 Name: Interrupt Disable Register IDR Access Type: Write-only Offset: 0x024 + n*0x040 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - TERR TRC RCZ Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR.
AT32UC3A3 18.7.15 Name: Interrupt Mask Register IMR Access Type: Read-only Offset: 0x028 + n*0x040 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - TERR TRC RCZ 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled.
AT32UC3A3 18.7.16 Name: Interrupt Status Register ISR Access Type: Read-only Offset: 0x02C + n*0x040 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - TERR TRC RCZ • TERR: Transfer Error This bit is cleared when no transfer errors have occurred since the last write to CR.ECLR.
AT32UC3A3 18.7.
AT32UC3A3 18.7.
AT32UC3A3 18.7.
AT32UC3A3 18.7.20 Name: Performance Channel 0 Read Max Latency PRLAT0 Access Type: Read/Write Offset: 0x80C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 3 2 1 0 LAT[15:8] 7 6 5 4 LAT[7:0] • LAT: Maximum Transfer Initiation Cycles Counted Since Last Reset Clock cycles are counted using the CLK_PDCA_HSB clock This counter is saturating.
AT32UC3A3 18.7.
AT32UC3A3 18.7.
AT32UC3A3 18.7.23 Name: Performance Channel 0 Write Max Latency PWLAT0 Access Type: Read/Write Offset: 0x818 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 3 2 1 0 LAT[15:8] 7 6 5 4 LAT[7:0] • LAT: Maximum Transfer Initiation Cycles Counted Since Last Reset Clock cycles are counted using the CLK_PDCA_HSB clock This counter is saturating.
AT32UC3A3 18.7.
AT32UC3A3 18.7.
AT32UC3A3 18.7.26 Name: Performance Channel 1 Read Max Latency PRLAT1 Access Type: Read/Write Offset: 0x824 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 3 2 1 0 LAT[15:8] 7 6 5 4 LAT[7:0] • LAT: Maximum Transfer Initiation Cycles Counted Since Last Reset Clock cycles are counted using the CLK_PDCA_HSB clock This counter is saturating.
AT32UC3A3 18.7.
AT32UC3A3 18.7.
AT32UC3A3 18.7.29 Name: Performance Channel 1 Write Max Latency PWLAT1 Access Type: Read/Write Offset: 0x830 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 3 2 1 0 LAT[15:8] 7 6 5 4 LAT[7:0] • LAT: Maximum Transfer Initiation Cycles Counted Since Last Reset Clock cycles are counted using the CLK_PDCA_HSB clock This counter is saturating.
AT32UC3A3 18.7.30 Name: PDCA Version Register VERSION Access Type: Read-only Offset: 0x834 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated.
AT32UC3A3 18.8 Module Configuration The specific configuration for the PDCA instance is listed in the following tables. Table 18-6. Features PDCA Number of channels 8 Table 18-7. 18.8.1 PDCA Configuration Register Reset Values Register Reset Value PSRn n VERSION 0x00000110 DMA Handshake Signals The table below defines the valid Peripheral Identifiers (PIDs).
AT32UC3A3 Table 18-8.
AT32UC3A3 19. DMA Controller (DMACA) Rev: 2.0.6.6 19.
AT32UC3A3 19.3 Block Diagram Figure 19-1. DMA Controller (DMACA) Block Diagram DMA Controller HSB Slave HSB Slave I/F Interrupt Generator CFG irq_dma Channel 1 Channel 0 FIFO HSB Master HSB Master I/F SRC FSM 19.4 DST FSM Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 19.4.1 I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with GPIO lines.
AT32UC3A3 19.5 19.5.1 Functional Description Basic Definitions Source peripheral: Device on a System Bus layer from where the DMACA reads data, which is then stored in the channel FIFO. The source peripheral teams up with a destination peripheral to form a channel. Destination peripheral: Device to which the DMACA writes the stored data from the FIFO (previously read from the source peripheral).
AT32UC3A3 Transfer hierarchy: Figure 19-2 on page 319 illustrates the hierarchy between DMACA transfers, block transfers, transactions (single or burst), and System Bus transfers (single or burst) for non-memory peripherals. Figure 19-3 on page 319 shows the transfer hierarchy for memory. Figure 19-2.
AT32UC3A3 – Single transaction: The length of a single transaction is always 1 and is converted to a single System Bus transfer. – Burst transaction: The length of a burst transaction is programmed into the DMACA. The burst transaction is converted into a sequence of System Bus bursts and single transfers. DMACA executes each burst transfer by performing incremental bursts that are no longer than the maximum System Bus burst size set.
AT32UC3A3 Gather is enabled by writing a ‘1’ to the CTLx.SRC_GATHER_EN bit. The CTLx.SINC field determines if the address is incremented, decremented or remains fixed when a gather boundary is reached. If the CTLx.SINC field indicates a fixed-address control throughout a DMA transfer, then the CTLx.SRC_GATHER_EN bit is ignored and the gather feature is automatically disabled.
AT32UC3A3 Figure 19-5. Source Gather Transfer System Memory D11 A0 + 0x034 A0 + 0x030 A0 + 0x02C A0 + 0x028 d11 D10 D9 D8 d8 A0 + 0x018 A0 + 0x014 D7 Data Stream d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 A0 + 0x020 A0 + 0x01C Gather Boundary A0 + 0x38 Gather Increment = 4 d7 Gather Boundary A0 + 0x24 Gather Increment = 4 D6 D5 d4 D4 A0 + 0x00C A0 + 0x008 A0 + 0x004 A0 D3 d3 Gather Boundary A0 + 0x10 Gather Increment = 4 D2 D1 D0 d0 CTLx.SRC_TR_WIDTH = 3'b010 (32bit/8 = 4 bytes) SGR.
AT32UC3A3 19.6 Arbitration for HSB Master Interface Each DMACA channel has two request lines that request ownership of a particular master bus interface: channel source and channel destination request lines. Source and destination arbitrate separately for the bus. Once a source/destination state machine gains ownership of the master bus interface and the master bus interface has ownership of the HSB bus, then HSB transfers can proceed between the peripheral and the DMACA.
AT32UC3A3 Software selects between the hardware or software handshaking interface on a per-channel basis. Software handshaking is accomplished through memory-mapped registers, while hardware handshaking is accomplished using a dedicated handshaking interface. 19.8.1 Software Handshaking When the slave peripheral requires the DMACA to perform a DMA transaction, it communicates this request by sending an interrupt to the CPU or interrupt controller.
AT32UC3A3 19.8.2.1 External DMA Request Definition When an external slave peripheral requires the DMACA to perform DMA transactions, it communicates its request by asserting the external nDMAREQx signal. This signal is resynchronized to ensure a proper functionality (see ”External DMA Request Timing” on page 325). The external nDMAREQx signal should be asserted when the source threshold level is reached. After resynchronization, the rising edge of dma_req starts the transfer.
AT32UC3A3 A block descriptor (LLI) consists of following registers, SARx, DARx, LLPx, CTL. These registers, along with the CFGx register, are used by the DMACA to set up and describe the block transfer. 19.9.1 19.9.1.1 Multi-block Transfers Block Chaining Using Linked Lists In this case, the DMACA re-programs the channel registers prior to the start of each block by fetching the block descriptor for that block from system memory. This is known as an LLI update.
AT32UC3A3 Table 19-1. Programming of Transfer Types and Channel Register Update Method (DMACA State Machine Table) LLP.
AT32UC3A3 blocks is a function of CTLx.LLP_S_EN, CFGx.RELOAD_SR, CTLx.LLP_D_EN, and CFGx.RELOAD_DS registers (see Figure 19-1 on page 317). Note: 19.9.1.4 Both SARx and DARx updates cannot be selected to be contiguous. If this functionality is required, the size of the Block Transfer (CTLx.BLOCK_TS) must be increased. If this is at the maximum value, use Row 10 of Table 19-1 on page 327 and setup the LLI.SARx address of the block descriptor to be equal to the end SARx address of the previous block.
AT32UC3A3 programmed to zero in the end of block interrupt service routine that services the next-to-last block transfer. This puts the DMACA into Row 1 state. For rows 6, 8, and 10 (both CFGx.RELOAD_SR and CFGx.RELOAD_DS cleared) the user must setup the last block descriptor in memory such that both LLI.CTLx.LLP_S_EN and LLI.CTLx.LLP_D_EN are zero. If the LLI.LLPx register of the last block descriptor in memory is non-zero, then the DMA transfer is terminated in Row 5. If the LLI.
AT32UC3A3 – ii. Set up the transfer characteristics, such as: – Transfer width for the source in the SRC_TR_WIDTH field. – Transfer width for the destination in the DST_TR_WIDTH field. – Source master layer in the SMS field where source resides. – Destination master layer in the DMS field where destination resides. – Incrementing/decrementing or fixed address for source in SINC field. – Incrementing/decrementing or fixed address for destination in DINC field. e.
AT32UC3A3 a. Designate the handshaking interface type (hardware or software) for the source and destination peripherals. This is not required for memory. This step requires programming the HS_SEL_SRC/HS_SEL_DST bits, respectively. Writing a ‘0’ activates the hardware handshaking interface to handle source/destination requests for the specific channel. Writing a ‘1’ activates the software handshaking interface to handle source/destination requests. b.
AT32UC3A3 Figure 19-8. Multi-Block with Linked List Address for Source and Destination Address of Destination Layer Address of Source Layer Block 2 SAR(2) Block 2 DAR(2) Block 1 SAR(1) Block 1 DAR(1) Block 0 Block 0 DAR(0) SAR(0) Source Blocks Destination Blocks If the user needs to execute a DMA transfer where the source and destination address are contiguous but the amount of data to be transferred is greater than the maximum block size CTLx.
AT32UC3A3 Figure 19-9. Multi-Block with Linked Address for Source and Destination Blocks are Contiguous Address of Source Layer Address of Destination Layer Block 2 DAR(3) Block 2 Block 2 SAR(3) DAR(2) Block 2 Block 1 SAR(2) DAR(1) Block 1 Block 0 SAR(1) DAR(0) Block 0 SAR(0) Source Blocks Destination Blocks The DMA transfer flow is shown in Figure 19-11 on page 336.
AT32UC3A3 Figure 19-10. DMA Transfer Flow for Source and Destination Linked List Address Channel enabled by software LLI Fetch Hardware reprograms SARx, DARx, CTLx, LLPx DMAC block transfer Source/destination status fetch Block Complete interrupt generated here Is DMAC in Row1 of DMAC State Machine Table? DMAC transfer Complete interrupt generated here no yes Channel Disabled by hardware 19.10.1.
AT32UC3A3 a. Write the starting source address in the SARx register for channel x. b. Write the starting destination address in the DARx register for channel x. c. Program CTLx and CFGx according to Row 4 as shown in Table 19-1 on page 327. Program the LLPx register with ‘0’. d. Write the control information for the DMA transfer in the CTLx register for channel x. For example, in the register, you can program the following: – i.
AT32UC3A3 should clear the reload bits in the CFGx.RELOAD_SR and CFGx.RELOAD_DS registers. This put the DMACA into Row 1 as shown in Table 19-1 on page 327. If the next block is not the last block in the DMA transfer, then the reload bits should remain enabled to keep the DMACA in Row 4. b. If interrupts are disabled (CTLx.
AT32UC3A3 Figure 19-12. DMA Transfer Flow for Source and Destination Address Auto-reloaded Channel Enabled by software Block Transfer Reload SARx, DARx, CTLx Block Complete interrupt generated here DMAC transfer Complete interrupt generated here yes Is DMAC in Row1 of DMAC State Machine Table? Channel Disabled by hardware no CTLx.INT_EN=1 && MASKBLOCK[x]=1? no yes Stall until block complete interrupt cleared by software 19.10.1.
AT32UC3A3 3. Write the starting source address in the SARx register for channel x. Note: The values in the LLI.SARx register locations of each of the Linked List Items (LLIs) setup up in memory, although fetched during a LLI fetch, are not used. 4. Write the channel configuration information into the CFGx register for channel x. a. Designate the handshaking interface type (hardware or software) for the source and destination peripherals. This is not required for memory.
AT32UC3A3 block complete interrupt when the block transfer has completed. It then stalls until the block complete interrupt is cleared by software. If the next block is to be the last block in the DMA transfer, then the block complete ISR (interrupt service routine) should clear the CFGx.RELOAD_SR source reload bit. This puts the DMACA into Row1 as shown in Table 19-1 on page 327.
AT32UC3A3 Figure 19-14. DMA Transfer Flow for Source Address Auto-reloaded and Linked List Destination Address Channel Enabled by software LLI Fetch Hardware reprograms DARx, CTLx, LLPx DMAC block transfer Source/destination status fetch Reload SARx Block Complete interrupt generated here DMAC Transfer Complete interrupt generated here yes Channel Disabled by hardware Is DMAC in Row1 or Row5 of DMAC State Machine Table? no CTLx.
AT32UC3A3 19.10.1.5 Multi-block Transfer with Source Address Auto-reloaded and Contiguous Destination Address (Row 3) 1. Read the Channel Enable register to choose a free (disabled) channel. 2. Clear any pending interrupts on the channel from the previous DMA transfer by writing a ‘1’ to the Interrupt Clear registers: ClearTfr, ClearBlock, ClearSrcTran, ClearDstTran, ClearErr. Reading the Interrupt Raw Status and Interrupt Status registers confirms that all interrupts have been cleared. 3.
AT32UC3A3 Reg.CH_EN) bit until it is cleared by hardware, to detect when the transfer is complete. If the DMACA is not in Row 1, the next step is performed. 7. The DMA transfer proceeds as follows: a. If interrupts are enabled (CTLx.INT_EN = 1) and the block complete interrupt is unmasked (MaskBlock[x] = 1’b1, where x is the channel number) hardware sets the block complete interrupt when the block transfer has completed. It then stalls until the block complete interrupt is cleared by software.
AT32UC3A3 Figure 19-16. DMA Transfer for Source Address Auto-reloaded and Contiguous Destination Address Channel Enabled by software Block Transfer Reload SARx, CTLx Block Complete interrupt generated here DMAC Transfer Complete interrupt generated here yes Channel Disabled by hardware Is DMAC in Row1 of DMAC State Machine Table? no CTLx.INT_EN=1 && MASKBLOCK[x]=1? no yes Stall until Block Complete interrupt cleared by software 19.10.1.
AT32UC3A3 – v. Incrementing/decrementing or fixed address for source in SINC field. – vi. Incrementing/decrementing or fixed address for destination DINC field. 3. Write the starting destination address in the DARx register for channel x. Note: The values in the LLI.DARx register location of each Linked List Item (LLI) in memory, although fetched during an LLI fetch, are not used. 4. Write the channel configuration information into the CFGx register for channel x. a.
AT32UC3A3 5 of Table 19-1 on page 327. The DMACA then knows that the previous block transferred was the last block in the DMA transfer. The DMACA transfer might look like that shown in Figure 19-17 on page 345 Note that the destination address is decrementing. Figure 19-17.
AT32UC3A3 Figure 19-19. DMA Transfer Flow for Source Address Auto-reloaded and Contiguous Destination Address Channel Enabled by software LLI Fetch Hardware reprograms SARx, CTLx, LLPx DMAC block transfer Source/destination status fetch Block Complete interrupt generated here Is DMAC in Row 1 of Table 4 ? DMAC Transfer Complete interrupt generated here no yes Channel Disabled by hardware 19.
AT32UC3A3 3. The ChEnReg.CH_EN bit can then be cleared by software once the channel FIFO is empty. When CTLx.SRC_TR_WIDTH is less than CTLx.DST_TR_WIDTH and the CFGx.CH_SUSP bit is high, the CFGx.FIFO_EMPTY is asserted once the contents of the FIFO do not permit a single word of CTLx.DST_TR_WIDTH to be formed. However, there may still be data in the channel FIFO but not enough to form a single transfer of CTLx.DST_TR_WIDTH width.
AT32UC3A3 19.12 User Interface Table 19-2.
AT32UC3A3 Table 19-2.
AT32UC3A3 19.12.1 Name: Channel x Source Address Register SARx Access Type: Read/Write Offset: 0x000 + [x * 0x58] Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 SADD[31:24] 23 22 21 20 SADD[23:16] 15 14 13 12 SADD[15:8] 7 6 5 4 SADD[7:0] • SADD: Source Address of DMA transfer The starting System Bus source address is programmed by software before the DMA channel is enabled or by a LLI update before the start of the DMA transfer.
AT32UC3A3 19.12.
AT32UC3A3 19.12.3 Name: Linked List Pointer Register for Channel x LLPx Access Type: Read/Write Offset: 0x010 + [x * 0x58] Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 LOC[29:22] 23 22 21 20 LOC[21:14] 15 14 13 12 LOC[13:6] 7 6 5 4 LOC[5:0] LMS • LOC: Address of the next LLI Starting address in memory of next LLI if block chaining is enabled.
AT32UC3A3 19.12.4 Name: Control Register for Channel x Low CTLxL Access Type: Read/Write Offset: 0x018 + [x * 0x58] Reset Value: 0x00304801 31 30 23 22 DMS[0] 29 21 28 27 LLP_SRC_E N LLP_DST_E N 20 19 TT_FC 15 14 13 SRC_MSIZE[1:0] 7 11 5 SRC_TR_WIDTH 4 25 SMS DMS[1] 17 16 DST_GATHE R_EN SRC_GATHE R_EN SRC_MSIZE [2] 10 9 8 SINC 3 24 18 DEST_MSIZE 6 DINC[0] 12 26 2 DINC[1] 1 DST_TR_WIDTH 0 INT_EN This register contains fields that control the DMA transfer.
AT32UC3A3 • DMS: Destination Master Select Identifies the Master Interface layer where the destination device (peripheral or memory) resides Table 19-5. Destination Master Select DMS HSB Master 0 HSB master 1 1 HSB master 2 Other Reserved • TT_FC: Transfer Type and Flow Control The four following transfer types are supported: • Memory to Memory, Memory to Peripheral, Peripheral to Memory and Peripheral to Peripheral. The DMACA is always the Flow Controller.
AT32UC3A3 SRC_MSIZE Size (items number) 3 16 4 32 Other Reserved • DST_MSIZE: Destination Burst Transaction Length Number of data items, each of width CTLx.DST_TR_WIDTH, to be written to the destination every time a destination burst transaction request is made from either the corresponding hardware or software handshaking interface.
AT32UC3A3 • SRT_TR_WIDTH: Source Transfer Width • DSC_TR_WIDTH: Destination Transfer Width SRC_TR_WIDTH/DST_TR_WIDTH Size (bits) 0 8 1 16 2 32 Other Reserved • INT_EN: Interrupt Enable Bit If set, then all five interrupt generating sources are enabled.
AT32UC3A3 19.12.
AT32UC3A3 19.12.
AT32UC3A3 0 = Hardware handshaking interface. Software-initiated transaction requests are ignored. 1 = Software handshaking interface. Hardware Initiated transaction requests are ignored. If the destination peripheral is memory, then this bit is ignored. • FIFO_EMPTY Indicates if there is data left in the channel's FIFO. Can be used in conjunction with CFGx.CH_SUSP to cleanly disable a channel.
AT32UC3A3 19.12.
AT32UC3A3 • FCMODE: Flow Control Mode Determines when source transaction requests are serviced when the Destination Peripheral is the flow controller. 0 = Source transaction requests are serviced when they occur. Data pre-fetching is enabled. 1 = Source transaction requests are not serviced until a destination transaction request occurs.
AT32UC3A3 19.12.8 Name: Source Gather Register for Channel x SGRx Access Type: Read/Write Offset: 0x048 + [x * 0x58] Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 SGC[11:4] 23 22 21 20 SGC[3:0] 15 14 SGI[19:16] 13 12 11 10 9 8 3 2 1 0 SGI[15:8] 7 6 5 4 SGI[7:0] • SGC: Source Gather Count Specifies the number of contiguous source transfers of CTLx.SRC_TR_WIDTH between successive gather intervals. This is defined as a gather boundary.
AT32UC3A3 19.12.9 Name: Destination Scatter Register for Channel x DSRx Access Type: Read/Write Offset: 0x050 + [x * 0x58] Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 DSC[11:4] 23 22 21 20 DSC[3:0] 15 14 DSI[19:16] 13 12 11 10 9 8 3 2 1 0 DSI[15:8] 7 6 5 4 DSI[7:0] • DSC: Destination Scatter Count Specifies the number of contiguous destination transfers of CTLx.DST_TR_WIDTH between successive scatter boundaries.
AT32UC3A3 19.12.10 Interrupt Registers The following sections describe the registers pertaining to interrupts, their status, and how to clear them. For each channel, there are five types of interrupt sources: • IntTfr: DMA Transfer Complete Interrupt This interrupt is generated on DMA transfer completion to the destination peripheral. • IntBlock: Block Transfer Complete Interrupt This interrupt is generated on DMA block transfer completion to the destination peripheral.
AT32UC3A3 19.12.
AT32UC3A3 19.12.
AT32UC3A3 19.12.
AT32UC3A3 19.12.
AT32UC3A3 19.12.
AT32UC3A3 19.12.16 Source Software Transaction Request Register Name: ReqSrcReg Access Type: Read/write Offset: 0x368 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - REQ_WE3 REQ_WE2 REQ_WE1 REQ_WE0 7 6 5 4 3 2 1 0 - - - - SRC_REQ3 SRC_REQ2 SRC_REQ1 SRC_REQ0 A bit is assigned for each channel in this register.
AT32UC3A3 19.12.17 Destination Software Transaction Request Register Name: ReqDstReg Access Type: Read/write Offset: 0x370 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - REQ_WE3 REQ_WE2 REQ_WE1 REQ_WE0 7 6 5 4 3 2 1 0 - - - - DST_REQ3 DST_REQ2 DST_REQ1 DST_REQ0 A bit is assigned for each channel in this register.
AT32UC3A3 19.12.18 Single Source Transaction Request Register Name: SglReqSrcReg Access Type: Read/write Offset: 0x378 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - REQ_WE3 REQ_WE2 REQ_WE1 REQ_WE0 7 6 5 4 3 2 1 0 - - - - S_SG_REQ3 S_SG_REQ2 S_SG_REQ1 S_SG_REQ0 A bit is assigned for each channel in this register.
AT32UC3A3 19.12.19 Single Destination Transaction Request Register Name: SglReqDstReg Access Type: Read/write Offset: 0x380 Reset Value: 0x0000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - REQ_WE3 REQ_WE2 REQ_WE1 REQ_WE0 7 6 5 4 3 2 1 0 - - - - D_SG_REQ3 D_SG_REQ2 D_SG_REQ1 D_SG_REQ0 A bit is assigned for each channel in this register.
AT32UC3A3 19.12.20 Last Source Transaction Request Register Name: LstSrcReg Access Type: Read/write Offset: 0x388 Reset Value: 0x0000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - LSTSRC_W E3 LSTSRC_W E2 LSTSRC_W E1 LSTSRC_W E0 7 6 5 4 3 2 1 0 - - - - LSTSRC3 LSTSRC2 LSTSRC1 LSTSRC0 A bit is assigned for each channel in this register.
AT32UC3A3 19.12.21 Last Destination Transaction Request Register Name: LstDstReg Access Type: Read/write Offset: 0x390 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - LSTDST_WE 3 LSTDST_WE 2 LSTDST_WE 1 LSTDST_WE 0 7 6 5 4 3 2 1 0 - - - - LSTDST3 LSTDST2 LSTDST1 LSTDST0 A bit is assigned for each channel in this register.
AT32UC3A3 19.12.22 DMA Configuration Register Name: DmaCfgReg Access Type: Read/Write Offset: 0x398 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - DMA_EN • DMA_EN: DMA Controller Enable 0 = DMACA Disabled 1 = DMACA Enabled.
AT32UC3A3 19.12.
AT32UC3A3 19.12.24 DMACA Component Id Register Low Name: DmaCompIdRegL Access Type: Read-only Offset: 0x3F8 Reset Value: 0x44571110 31 30 29 28 27 26 25 24 18 17 16 10 9 8 2 1 0 DMA_COMP_TYPE[31:24] 23 22 21 20 19 DMA_COMP_TYPE[23:16] 15 14 13 12 11 DMA_COMP_TYPE[15:8] 7 6 5 4 3 DMA_COMP_TYPE[7:0] • DMA_COMP_TYPE DesignWare component type number = 0x44571110.
AT32UC3A3 19.12.
AT32UC3A3 19.13 Module Configuration The following table defines the valid settings for the DEST_PER and SRC_PER fields in the CFGxH register. The direction is specified as observed from the DMACA. So for instance, AES RX means this hardware handshaking interface is connected to the input of the AES modulel Table 19-6. DMACA Handshake Interfaces PER Value Hardware Handshaking Interface 0 AES - RX 1 AES - TX 2 MCI - RX 3 MCI -TX 4 MSI - RX 5 MSI - TX 6 DMACA - EXT0 7 DMACA - EXT1 .
AT32UC3A3 20. General-Purpose Input/Output Controller (GPIO) Rev: 1.1.0.4 20.1 Features • • • • • 20.
AT32UC3A3 20.4.1 Module Configuration Most of the features of the GPIO are configurable for each product. The user must refer to the Package and Pinout chapter for these settings. Product specific settings includes: • Number of I/O pins. • Functions implemented on each pin • Peripheral function(s) multiplexed on each I/O pin • Reset value of registers 20.4.2 Clocks The clock for the GPIO bus interface (CLK_GPIO) is generated by the Power Manager.
AT32UC3A3 Figure 20-2. Overview of the GPIO Pad Connections ODER PUER 1 Periph. A output enable Periph. B output enable 0 Periph. C output enable Periph. D output enable PMR1 GPER PMR0 Periph. A output data Periph. B output data 0 Periph. C output data Periph. D output data PAD 1 OVR Periph. A input data Periph. B input data Periph. C input data PVR Periph. D input data IER 0 Edge Detector Glitch Filter IMR1 GFER 20.5.1 1 1 0 Interrupt Request IMR0 Basic Operation 20.5.1.
AT32UC3A3 responding I/O line is driven by the GPIO. When the bit is written to zero, the GPIO does not drive the line. The level driven on an I/O line can be determined by writing to the Output Value Register (OVR). 20.5.1.4 Inputs The level on each I/O line can be read through the Pin Value Register (PVR). This register indicates the level of the I/O lines regardless of whether the lines are driven by the GPIO or by an external component.
AT32UC3A3 20.5.3 Interrupts The GPIO can be configured to generate an interrupt when it detects an input change on an I/O line. The module can be configured to signal an interrupt whenever a pin changes value or only to trigger on rising edges or falling edges. Interrupts are enabled on a pin by writing a one to the corresponding bit in the Interrupt Enable Register (IER). The interrupt mode is set by writing to the Interrupt Mode Register 0 (IMR0) and the Interrupt Mode Register 1(IMR1).
AT32UC3A3 20.6 User Interface The GPIO controls all the I/O pins on the AVR32 microcontroller. The pins are managed as 32bit ports that are configurable through a PB interface. Each port has a set of configuration registers. The overall memory map of the GPIO is shown below. The number of pins and hence the number of ports are product specific. Figure 20-6.
AT32UC3A3 register offset and the port offset to the GPIO start address. One bit in each of the configuration registers corresponds to an I/O pin. Table 20-1.
AT32UC3A3 Table 20-1.
AT32UC3A3 20.6.2 Name: Enable Register GPER Access Type: Read, Write, Set, Clear, Toggle Offset: 0x00, 0x04, 0x08, 0x0C Reset Value: - 31 30 29 28 27 26 P31 P30 P29 P28 P27 P26 25 24 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Pin Enable 0: A peripheral function controls the corresponding pin.
AT32UC3A3 20.6.
AT32UC3A3 20.6.
AT32UC3A3 20.6.
AT32UC3A3 20.6.6 Name: Output Value Register OVR Access Type: Read, Write, Set, Clear, Toggle Offset: 0x50, 0x54, 0x58, 0x5C Reset Value: - 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-31: Output Value 0: The value to be driven on the I/O line is 0.
AT32UC3A3 20.6.7 Name: Pin Value Register PVR Access Type: Read Offset: 0x60, 0x64, 0x68, 0x6C Reset Value: - 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-31: Pin Value 0: The I/O line is at level ‘0’. 1: The I/O line is at level ‘1’.
AT32UC3A3 20.6.
AT32UC3A3 20.6.9 Name: Interrupt Enable Register IER Access Type: Read, Write, Set, Clear, Toggle Offset: 0x90, 0x94, 0x98, 0x9C Reset Value: - 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-31: Interrupt Enable 0: Interrupt is disabled for the corresponding pin.
AT32UC3A3 20.6.
AT32UC3A3 20.6.
AT32UC3A3 20.6.12 Name: Glitch Filter Enable Register GFER Access Type: Read, Write, Set, Clear, Toggle Offset: 0xC0, 0xC4, 0xC8, 0xCC Reset Value: - 31 30 29 28 27 26 P31 P30 P29 P28 P27 P26 25 24 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-31: Glitch Filter Enable 0: Glitch filter is disabled for the corresponding pin.
AT32UC3A3 20.6.13 Name: Interrupt Flag Register IFR Access Type: Read, Clear Offset: 0xD0, 0xD8 Reset Value: - 31 30 29 28 27 26 P31 P30 P29 P28 P27 P26 25 24 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-31: Interrupt Flag 1: An interrupt condition has been detected on the corresponding pin.
AT32UC3A3 20.7 20.7.1 Programming Examples 8-bit LED-Chaser // Set R0 to GPIO base address mov R0, LO(AVR32_GPIO_ADDRESS) orh R0, HI(AVR32_GPIO_ADDRESS) // Enable GPIO control of pin 0-8 mov R1, 0xFF st.w R0[AVR32_GPIO_GPERS], R1 // Set initial value of port mov R2, 0x01 st.w R0[AVR32_GPIO_OVRS], R2 // Set up toggle value. Two pins are toggled // in each round. The bit that is currently set, // and the next bit to be set.
AT32UC3A3 mov R1, 0x0000 orh R1, 0x0003 st.w R0[AVR32_GPIO_ODERC], R1 // Make the GPIO control the pins st.w R0[AVR32_GPIO_GPERS], R1 // Select peripheral B on PC16-PC17 st.w R0[AVR32_GPIO_PMR0S], R1 st.w R0[AVR32_GPIO_PMR1C], R1 // Enable peripheral control st.
AT32UC3A3 20.8 Module configuration The specific configuration for each GPIO instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks according to the table in the System Bus Clock Connections section. Table 20-2. Module configuration Feature GPIO Number of GPIO ports 4 Number of peripheral functions 4 Table 20-3.
AT32UC3A3 21. Serial Peripheral Interface (SPI) Rev: 2.1.0.3 21.
AT32UC3A3 21.3 Block Diagram Figure 21-1. SPI Block Diagram Peripheral DMA Controller Peripheral Bus SPCK MISO CLK_SPI MOSI Spi Interface I/O Controller NPCS0/NSS NPCS1 NPCS2 Interrupt Control NPCS3 SPI Interrupt 21.4 Application Block Diagram Figure 21-2.
AT32UC3A3 21.5 I/O Lines Description Table 21-1. I/O Lines Description Type 21.6 Pin Name Pin Description Master Slave MISO Master In Slave Out Input Output MOSI Master Out Slave In Output Input SPCK Serial Clock Output Input NPCS1-NPCS3 Peripheral Chip Selects Output Unused NPCS0/NSS Peripheral Chip Select/Slave Select Output Input Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 21.6.
AT32UC3A3 21.7.2 Data Transfer Four combinations of polarity and phase are available for data transfers. The clock polarity is configured with the Clock Polarity bit in the Chip Select Registers (CSRn.CPOL). The clock phase is configured with the Clock Phase bit in the CSRn registers (CSRn.NCPHA). These two bits determine the edges of the clock signal on which data is driven and sampled.
AT32UC3A3 Figure 21-4. SPI Transfer Format (NCPHA = 0, 8 bits per transfer) SPCK cycle (for reference) 1 2 3 4 5 6 7 8 SPCK (CPOL = 0) SPCK (CPOL = 1) MOSI (from master) MISO (from slave) *** MSB 6 5 4 3 2 1 MSB 6 5 4 3 2 1 LSB LSB NSS (to slave) *** Not Defined, but normaly LSB of previous character transmitted 21.7.3 Master Mode Operations When configured in master mode, the SPI uses the internal programmable baud rate generator as clock source.
AT32UC3A3 In master mode, if the received data is not read fast enough compared to the transfer rhythm imposed by the write accesses in the TDR, some overrun errors may occur, even if the FIFO is enabled. To insure a perfect data integrity of received data (especially at high data rate), the mode Wait Data Read Before Transfer can be enabled in the MR register (MR.WDRBT). When this mode is activated, no transfer starts while received data remains unread in the RDR.
AT32UC3A3 21.7.3.2 Master mode flow diagram Figure 21-6. Master Mode Flow Diagram SPI Enable - NPCS defines the current Chip Select - CSAAT, DLYBS, DLYBCT refer to the fields of the Chip Select Register corresponding to the Current Chip Select - When NPCS is 0xF, CSAAT is 0.
AT32UC3A3 21.7.3.3 Clock generation The SPI Baud rate clock is generated by dividing the CLK_SPI , by a value between 1 and 255. This allows a maximum operating baud rate at up to CLK_SPI and a minimum operating baud rate of CLK_SPI divided by 255. Writing the Serial Clock Baud Rate field in the CSRn registers (CSRn.SCBR) to zero is forbidden. Triggering a transfer while CSRn.SCBR is zero can lead to unpredictable results. At reset, CSRn.
AT32UC3A3 21.7.3.5 Peripheral selection The serial peripherals are selected through the assertion of the NPCS0 to NPCS3 signals. By default, all the NPCS signals are high before and after each transfer.
AT32UC3A3 to an interrupt, and thus might lead to difficulties for interfacing with some serial peripherals requiring the chip select line to remain active during a full set of transfers. To facilitate interfacing with such devices, the CSRn registers can be configured with the Chip Select Active After Transfer bit written to one (CSRn.CSAAT) . This allows the chip select lines to remain in their current state (low = active) until transfer to another peripheral is required. When the CSRn.
AT32UC3A3 Figure 21-8. Peripheral Deselection CSAAT = 0 and CSNAAT = 0 TDRE CSAAT = 1 and CSNAAT= 0 / 1 DLYBCT NPCS[0..3] DLYBCT A A A A DLYBCS A DLYBCS PCS = A PCS = A Write TDR TDRE DLYBCT DLYBCT A NPCS[0..3] A A A DLYBCS A DLYBCS PCS=A PCS = A Write TDR TDRE DLYBCT NPCS[0..3] DLYBCT A B B A DLYBCS DLYBCS PCS = B PCS = B Write TDR CSAAT = 0 and CSNAAT = 0 CSAAT = 0 and CSNAAT = 1 DLYBCT DLYBCT TDRE A NPCS[0..
AT32UC3A3 register (MR.MODFDIS). In systems with open-drain I/O lines, a mode fault is detected when a low level is driven by an external master on the NPCS0/NSS signal. When a mode fault is detected, the Mode Fault Error bit in the SR (SR.MODF) is set until the SR is read and the SPI is automatically disabled until re-enabled by writing a one to the SPI Enable bit in the CR register (CR.SPIEN). By default, the mode fault detection circuitry is enabled.
AT32UC3A3 Figure 21-9.
AT32UC3A3 21.8 User Interface Table 21-3.
AT32UC3A3 21.8.1 Name: Control Register CR Access Type: Write-only Offset: 0x00 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - LASTXFER 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - FLUSHFIFO 7 6 5 4 3 2 1 0 SWRST - - - - - SPIDIS SPIEN • LASTXFER: Last Transfer 1: The current NPCS will be deasserted after the character written in TD has been transferred. When CSRn.
AT32UC3A3 21.8.2 Name: Mode Register MR Access Type: Read/Write Offset: 0x04 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 DLYBCS 23 22 21 20 - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 LLB RXFIFOEN WDRBT- MODFDIS - PCSDEC PS MSTR PCS • DLYBCS: Delay Between Chip Selects This field defines the delay from NPCS inactive to the activation of another NPCS.
AT32UC3A3 0: The FIFO is not used in reception (only one character can be stored in the SPI). • WDRBT: Wait Data Read Before Transfer 1: In master mode, a transfer can start only if the RDR register is empty, i.e. does not contain any unread data. This mode prevents overrun error in reception. 0: No Effect. In master mode, a transfer can be initiated whatever the state of the RDR register is. • MODFDIS: Mode Fault Detection 1: Mode fault detection is disabled.
AT32UC3A3 21.8.3 Name: Receive Data Register RDR Access Type: Read-only Offset: 0x08 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 3 2 1 0 RD[15:8] 7 6 5 4 RD[7:0] • RD: Receive Data Data received by the SPI Interface is stored in this register right-justified. Unused bits read zero.
AT32UC3A3 21.8.4 Name: Transmit Data Register TDR Access Type: Write-only Offset: 0x0C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - LASTXFER 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 PCS 11 10 9 8 3 2 1 0 TD[15:8] 7 6 5 4 TD[7:0] • LASTXFER: Last Transfer 1: The current NPCS will be deasserted after the character written in TD has been transferred. When CSRn.
AT32UC3A3 21.8.5 Name: Status Register SR Access Type: Read-only Offset: 0x10 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - SPIENS 15 14 13 12 11 10 9 8 - - - - - UNDES TXEMPTY NSSR 7 6 5 4 3 2 1 0 - - - - OVRES MODF TDRE RDRF • SPIENS: SPI Enable Status 1: This bit is set when the SPI is enabled. 0: This bit is cleared when the SPI is disabled.
AT32UC3A3 21.8.6 Name: Interrupt Enable Register IER Access Type: Write-only Offset: 0x14 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - UNDES TXEMPTY NSSR 7 6 5 4 3 2 1 0 - - - - OVRES MODF TDRE RDRF Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR.
AT32UC3A3 21.8.7 Name: Interrupt Disable Register IDR Access Type: Write-only Offset: 0x18 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - UNDES TXEMPTY NSSR 7 6 5 4 3 2 1 0 - - - - OVRES MODF TDRE RDRF Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR.
AT32UC3A3 21.8.8 Name: Interrupt Mask Register IMR Access Type: Read-only Offset: 0x1C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - UNDES TXEMPTY NSSR 7 6 5 4 3 2 1 0 - - - - OVRES MODF TDRE RDRF 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled.
AT32UC3A3 21.8.9 Name: Chip Select Register 0 CSR0 Access Type: Read/Write Offset: 0x30 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CSAAT CSNAAT NCPHA CPOL DLYBCT 23 22 21 20 DLYBS 15 14 13 12 SCBR 7 6 5 BITS 4 • DLYBCT: Delay Between Consecutive Transfers This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select.
AT32UC3A3 • BITS: Bits Per Transfer The BITS field determines the number of data bits transferred. Reserved values should not be used. BITS Bits Per Transfer 0000 8 0001 9 0010 10 0011 11 0100 12 0101 13 0110 14 0111 15 1000 16 1001 4 1010 5 1011 6 1100 7 1101 Reserved 1110 Reserved 1111 Reserved • CSAAT: Chip Select Active After Transfer 1: The Peripheral Chip Select does not rise after the last transfer is achieved.
AT32UC3A3 CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce the required clock/data relationship between master and slave devices.
AT32UC3A3 21.8.10 Name: Chip Select Register 1 CSR1 Access Type: Read/Write Offset: 0x34 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CSAAT CSNAAT NCPHA CPOL DLYBCT 23 22 21 20 DLYBS 15 14 13 12 SCBR 7 6 5 BITS 4 • DLYBCT: Delay Between Consecutive Transfers This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select.
AT32UC3A3 • BITS: Bits Per Transfer The BITS field determines the number of data bits transferred. Reserved values should not be used. BITS Bits Per Transfer 0000 8 0001 9 0010 10 0011 11 0100 12 0101 13 0110 14 0111 15 1000 16 1001 4 1010 5 1011 6 1100 7 1101 Reserved 1110 Reserved 1111 Reserved • CSAAT: Chip Select Active After Transfer 1: The Peripheral Chip Select does not rise after the last transfer is achieved.
AT32UC3A3 CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce the required clock/data relationship between master and slave devices.
AT32UC3A3 21.8.11 Name: Chip Select Register 2 CSR2 Access Type: Read/Write Offset: 0x38 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CSAAT CSNAAT NCPHA CPOL DLYBCT 23 22 21 20 DLYBS 15 14 13 12 SCBR 7 6 5 BITS 4 • DLYBCT: Delay Between Consecutive Transfers This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select.
AT32UC3A3 • BITS: Bits Per Transfer The BITS field determines the number of data bits transferred. Reserved values should not be used. BITS Bits Per Transfer 0000 8 0001 9 0010 10 0011 11 0100 12 0101 13 0110 14 0111 15 1000 16 1001 4 1010 5 1011 6 1100 7 1101 Reserved 1110 Reserved 1111 Reserved • CSAAT: Chip Select Active After Transfer 1: The Peripheral Chip Select does not rise after the last transfer is achieved.
AT32UC3A3 CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce the required clock/data relationship between master and slave devices.
AT32UC3A3 21.8.12 Name: Chip Select Register 3 CSR3 Access Type: Read/Write Offset: 0x3C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CSAAT CSNAAT NCPHA CPOL DLYBCT 23 22 21 20 DLYBS 15 14 13 12 SCBR 7 6 5 BITS 4 • DLYBCT: Delay Between Consecutive Transfers This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select.
AT32UC3A3 • BITS: Bits Per Transfer The BITS field determines the number of data bits transferred. Reserved values should not be used. BITS Bits Per Transfer 0000 8 0001 9 0010 10 0011 11 0100 12 0101 13 0110 14 0111 15 1000 16 1001 4 1010 5 1011 6 1100 7 1101 Reserved 1110 Reserved 1111 Reserved • CSAAT: Chip Select Active After Transfer 1: The Peripheral Chip Select does not rise after the last transfer is achieved.
AT32UC3A3 CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce the required clock/data relationship between master and slave devices.
AT32UC3A3 21.8.
AT32UC3A3 21.8.
AT32UC3A3 • SPIWPVS: SPI Write Protection Violation Status SPIWPVS value Violation Type 1 The Write Protection has blocked a Write access to a protected register (since the last read). 2 Software Reset has been performed while Write Protection was enabled (since the last read or since the last write access on MR, IER, IDR or CSRx). 3 Both Write Protection violation and software reset with Write Protection enabled have occurred since the last read.
AT32UC3A3 21.8.15 Version Register Register Name: VERSION Access Type: Read-only Offset: 0xFC Reset Value: – 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 MFN 11 10 VERSION[11:8] 7 6 5 4 3 2 1 0 VERSION[7:0] • MFN Reserved. No functionality associated. • VERSION Version number of the module. No functionality associated.
AT32UC3A3 21.9 Module Configuration The specific configuration for each SPI instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager section for details. Table 21-4. Module Clock Name Module Name Clock Name SPI0 CLK_SPI0 SPI1 CLK_SPI1 Table 21-5.
AT32UC3A3 22. Two-wire Slave Interface (TWIS) Rev.: 1.0.0.1 22.1 Features • Compatible with I²C standard • • • • • • 22.
AT32UC3A3 Below, Table 22-2 lists the compatibility level of the Atmel Two-wire Slave Interface and a full SMBus compatible device. Table 22-2. 22.3 SMBus Standard Atmel TWIS Bus Timeouts Supported Address Resolution Protocol Supported Alert Supported Packet Error Checking Supported List of Abbreviations Table 22-3. 22.
AT32UC3A3 22.5 Application Block Diagram Figure 22-2. Application Block Diagram VDD Rp Host with TWI Interface Rp TWD TWCK Atmel TWI serial EEPROM Slave 1 I²C RTC I²C LCD controller I²C temp. sensor Slave 2 Slave 3 Slave 4 Rp: Pull up value as given by the I²C Standard 22.6 I/O Lines Description Table 22-4. I/O Lines Description Pin Name Pin Description TWD Two-wire Serial Data Input/Output TWCK Two-wire Serial Clock Input/Output TWALM SMBus SMBALERT Input/Output 22.
AT32UC3A3 22.7.2 Power Management If the CPU enters a sleep mode that disables clocks used by the TWIS, the TWIS will stop functioning and resume operation after the system wakes up from sleep mode. 22.7.3 Clocks The clock for the TWIS bus interface (CLK_TWIS) is generated by the Power Manager. This clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the TWIS before disabling the clock, to avoid freezing the TWIS in an undefined state. 22.7.
AT32UC3A3 Figure 22-4. Transfer Format TWD TWCK Start 22.8.2 Address R/W Ack Data Ack Data Ack Stop Operation The TWIS has two modes of operation: • Slave transmitter mode • Slave receiver mode A master is a device which starts and stops a transfer and generates the TWCK clock. A slave is assigned an address and responds to requests from the master. These modes are described in the following chapters. Figure 22-5.
AT32UC3A3 TTOUT: Prescaled clock cycles used to time SMBUS timeout TTIMEOUT. SUDAT: Non-prescaled clock cycles for data setup and hold count. Used to time TSU_DAT. EXP: Specifies the clock prescaler setting used for the SMBUS timeouts. Figure 22-6. Bus Timing Diagram t HIGH t LOW S t HD:STA t LOW t SU:DAT t HD:DAT t t 22.8.2.2 t SU:DAT SU:STA SU:STO P Sr Setting Up and Performing a Transfer Operation of the TWIS is mainly controlled by the Control Register (CR).
AT32UC3A3 In I²C mode: • The address in CR.ADR is checked for address match if CR.SMATCH is one. • The General Call address is checked for address match if CR.GCMATCH is one. In SMBus mode: • The address in CR.ADR is checked for address match if CR.SMATCH is one. • The Alert Response Address is checked for address match if CR.SMAL is one. • The Default Address is checked for address match if CR.SMDA is one. • The Host Header Address is checked for address match if CR.SMHH is one. 22.8.2.
AT32UC3A3 4. NBYTES is updated. If CR.CUP is one, NBYTES is incremented, otherwise NBYTES is decremented. 5. After each data byte has been transmitted, the master transmits an ACK (Acknowledge) or NAK (Not Acknowledge) bit. If a NAK bit is received by the TWIS, the SR.NAK bit is set. Note that this is done two CLK_TWIS cycles after TWCK has been sampled by the TWIS to be HIGH (see Figure 22-9). The NAK indicates that the transfer is finished, and the TWIS will wait for a STOP or REPEATED START.
AT32UC3A3 Figure 22-8. Slave Transmitter with Multiple Data Bytes TWD S DADR R A DATA n A DATA n+5 A DATA n+m N P TCOMP TXRDY Write THR (Data n) NBYTES set to m Write THR (Data n+1) Write THR (Data n+m) Last data sent STOP sent by master Figure 22-9. Timing Relationship between TWCK, SR.NAK, and SR.BTF TWD DATA (LSB) N P TWCK SR.NAK SR.BTF t1 t1 t1: (CLK_TWIS period) x 2 22.8.
AT32UC3A3 slave to pull it down in order to generate the acknowledge. The master polls the data line during this clock pulse. The SR.RXRDY bit indicates that a data byte is available in the RHR. The RXRDY bit is also used as Receive Ready for the Peripheral DMA Controller receive channel. Figure 22-10. Slave Receiver with One Data Byte TWD S DADR W A DATA A P TCOMP RXRDY Read RHR Figure 22-11.
AT32UC3A3 3. Start the transfer by enabling the Peripheral DMA Controller to receive. 4. Wait for the Peripheral DMA Controller end-of-receive flag. 5. Disable the Peripheral DMA Controller. 22.8.6 SMBus Mode SMBus mode is enabled by writing a one to the SMBus Mode Enable (SMEN) bit in CR. SMBus mode operation is similar to I²C operation with the following exceptions: • Only 7-bit addressing can be used. • The SMBus standard describes a set of timeout values to ensure progress and throughput on the bus.
AT32UC3A3 22.8.7 Identifying Bus Events This chapter lists the different bus events, and how these affects the bits in the TWIS registers. This is intended to help writing drivers for the TWIS. Table 22-5. Bus Events Event Effect Slave transmitter has sent a data byte SR.THR is cleared. SR.BTF is set. The value of the ACK bit sent immediately after the data byte is given by CR.ACK. Slave receiver has received a data byte SR.RHR is set. SR.BTF is set. SR.
AT32UC3A3 Table 22-5. Bus Events Event Effect Data is to be received in slave receiver mode, SR.STREN is cleared, and RHR is full TWCK is not stretched, read data is discarded. SR.ORUN is set. Data is to be transmitted in slave receiver mode, SR.STREN is cleared, and THR is empty TWCK is not stretched, previous contents of THR is written to bus. SR.URUN is set. SMBus timeout received SR.SMBTOUT is set. TWCK and TWD are immediately released.
AT32UC3A3 22.9 User Interface Table 22-6.
AT32UC3A3 22.9.1 Name: Control Register CR Access Type: Read/Write Offset: 0x00 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - TENBIT 23 22 21 20 19 18 17 16 ADR[9:8] ADR[7:0] 15 14 13 12 11 10 9 8 SOAM CUP ACK PECEN SMHH SMDA SMBALERT 7 6 5 4 3 2 1 0 SWRST - - STREN GCMATCH SMATCH SMEN SEN • TENBIT: Ten Bit Address Match 0: Disables Ten Bit Address Match. 1: Enables Ten Bit Address Match.
AT32UC3A3 Writing a one to this bit resets the TWIS. • STREN: Clock Stretch Enable 0: Disables clock stretching if RHR/THR buffer full/empty. May cause over/underrun. 1: Enables clock stretching if RHR/THR buffer full/empty. • GCMATCH: General Call Address Match 0: Causes the TWIS not to acknowledge the General Call Address. 1: Causes the TWIS to acknowledge the General Call Address. • SMATCH: Slave Address Match 0: Causes the TWIS not to acknowledge the Slave Address.
AT32UC3A3 22.9.2 Name: NBYTES Register NBYTES Access Type: Read/Write Offset: 0x04 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 NBYTES • NBYTES: Number of Bytes to Transfer Writing to this field updates the NBYTES counter. The field can also be read to learn the progress of the transfer.
AT32UC3A3 22.9.3 Name: Timing Register TR Access Type: Read/Write Offset: 0x08 Reset Value: 0x00000000 31 30 29 28 EXP 23 22 21 20 27 26 25 24 - - - - 19 18 17 16 11 10 9 8 3 2 1 0 SUDAT 15 14 13 12 TTOUT 7 6 5 4 TLOWS • EXP: Clock Prescaler Used to specify how to prescale the SMBus TLOWS counter.
AT32UC3A3 22.9.4 Name: Receive Holding Register RHR Access Type: Read-only Offset: 0x0C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 RXDATA • RXDATA: Received Data Byte When the RXRDY bit in the Status Register (SR) is one, this field contains a byte received from the TWI bus.
AT32UC3A3 22.9.5 Name: Transmit Holding Register THR Access Type: Write-only Offset: 0x10 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 TXDATA • TXDATA: Data Byte to Transmit Write data to be transferred on the TWI bus here.
AT32UC3A3 22.9.6 Name: Packet Error Check Register PECR Access Type: Read-only Offset: 0x14 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 PEC • PEC: Calculated PEC Value The calculated PEC value. Updated automatically by hardware after each byte has been transferred. Reset by hardware after a STOP condition.
AT32UC3A3 22.9.7 Name: Status Register SR Access Type: Read-only Offset: 0x18 Reset Value: 0x000000002 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 BTF REP STO SMBDAM SMBHHM SMBALERTM GCM SAM 15 14 13 12 11 10 9 8 - BUSERR SMBPECERR SMBTOUT - - - NAK 7 6 5 4 3 2 1 0 ORUN URUN TRA - TCOMP SEN TXRDY RXRDY • BTF: Byte Transfer Finished This bit is cleared when the corresponding bit in SCR is written to one.
AT32UC3A3 • SMBPECERR: SMBus PEC Error This bit is cleared when the corresponding bit in SCR is written to one. This bit is set when a SMBus PEC error has occurred. • SMBTOUT: SMBus Timeout This bit is cleared when the corresponding bit in SCR is written to one. This bit is set when a SMBus timeout has occurred. • NAK: NAK Received This bit is cleared when the corresponding bit in SCR is written to one. This bit is set when a NAK was received from the master during slave transmitter operation.
AT32UC3A3 22.9.8 Name: Interrupt Enable Register IER Access Type: Write-only Offset: 0x1C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 BTF REP STO SMBDAM SMBHHM SMBALERTM GCM SAM 15 14 13 12 11 10 9 8 - BUSERR SMBPECERR SMBTOUT - - - NAK 7 6 5 4 3 2 1 0 ORUN URUN - - TCOMP - TXRDY RXRDY Writing a zero to a bit in this register has no effect.
AT32UC3A3 22.9.9 Name: Interrupt Disable Register IDR Access Type: Write-only Offset: 0x20 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 BTF REP STO SMBDAM SMBHHM SMBALERTM GCM SAM 15 14 13 12 11 10 9 8 - BUSERR SMBPECERR SMBTOUT - - - NAK 7 6 5 4 3 2 1 0 ORUN URUN - - TCOMP - TXRDY RXRDY Writing a zero to a bit in this register has no effect.
AT32UC3A3 22.9.10 Name: Interrupt Mask Register IMR Access Type: Read-only Offset: 0x24 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 BTF REP STO SMBDAM SMBHHM SMBALERTM GCM SAM 15 14 13 12 11 10 9 8 - BUSERR SMBPECERR SMBTOUT - - - NAK 7 6 5 4 3 2 1 0 ORUN URUN - - TCOMP - TXRDY RXRDY 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled.
AT32UC3A3 22.9.11 Name: Status Clear Register SCR Access Type: Write-only Offset: 0x28 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 BTF REP STO SMBDAM SMBHHM SMBALERTM GCM SAM 15 14 13 12 11 10 9 8 - BUSERR SMBPECERR SMBTOUT - - - NAK 7 6 5 4 3 2 1 0 ORUN URUN - - TCOMP - - - Writing a zero to a bit in this register has no effect.
AT32UC3A3 22.9.
AT32UC3A3 22.9.13 Name: Version Register (VR) VR Access Type: Read-only Offset: 0x30 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION [11:8] 3 2 1 0 VERSION [7:0] • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated.
AT32UC3A3 22.10 Module Configuration The specific configuration for each TWIS instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks according to the table in the Power Manager section. Table 22-7. Module Clock Name Module name Clock name TWIS0 CLK_TWIS0 TWIS1 CLK_TWIS1 Table 22-8.
AT32UC3A3 23. Two-wire Master Interface (TWIM) Rev.: 1.0.0.1 23.1 Features • Compatible with I²C standard • • • • • • 23.
AT32UC3A3 Table 23-2 lists the compatibility level of the Atmel Two-wire Master Interface and a full SMBus compatible master. Table 23-2. 23.3 SMBus Standard Atmel TWIM Bus Timeouts Supported Address Resolution Protocol Supported Alert Supported Host Functionality Supported Packet Error Checking Supported List of Abbreviations Table 23-3. 23.
AT32UC3A3 23.5 Application Block Diagram Figure 23-2. Application Block Diagram VDD Rp Rp Rp TWD TWI Master TWCK TWALM Atmel TWI serial EEPROM I2C RTC I2C LCD controller I2C temp sensor Slave 1 Slave 2 Slave 3 Slave 4 Rp: pull-up value as given by the I2C Standard 23.6 I/O Lines Description Table 23-4. I/O Lines Description Pin Name Pin Description TWD Two-wire Serial Data Input/Output TWCK Two-wire Serial Clock Input/Output TWALM SMBus SMBALERT Input/Output 23.
AT32UC3A3 23.7.3 Clocks The clock for the TWIM bus interface (CLK_TWIM) is generated by the Power Manager. This clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the TWIM before disabling the clock, to avoid freezing the TWIM in an undefined state. 23.7.4 DMA The TWIM DMA handshake interface is connected to the Peripheral DMA Controller. Using the TWIM DMA functionality requires the Peripheral DMA Controller to be programmed after setting up the TWIM. 23.
AT32UC3A3 23.8 23.8.1 Functional Description Transfer Format The data put on the TWD line must be 8 bits long. Data is transferred MSB first; each byte must be followed by an acknowledgement. The number of bytes per transfer is unlimited (see Figure 23-4). Each transfer begins with a START condition and terminates with a STOP condition (see Figure 23-4). • A high-to-low transition on the TWD line while TWCK is high defines the START condition.
AT32UC3A3 23.8.2.1 Clock Generation The Clock Waveform Generator Register (CWGR) is used to control the waveform of the TWCK clock. CWGR must be written so that the desired TWI bus timings are generated. CWGR describes bus timings as a function of cycles of a prescaled clock. The clock prescaling can be selected through the Clock Prescaler field in CWGR (CWGR.EXP). f CLK_TWIM f PRESCALER = ------------------------( EXP + 1 ) 2 CWGR has the following fields: LOW: Prescaled clock cycles in clock low count.
AT32UC3A3 23.8.2.2 Setting up and Performing a Transfer Operation of the TWIM is mainly controlled by the Control Register (CR) and the Command Register (CMDR). TWIM status is provided in the Status Register (SR). The following list presents the main steps in a typical communication: 1. Before any transfers can be performed, bus timings must be configured by writing to the Clock Waveform Generator Register (CWGR).
AT32UC3A3 TWI transfers require the slave to acknowledge each received data byte. During the acknowledge clock pulse (9th pulse), the master releases the data line (HIGH), enabling the slave to pull it down in order to generate the acknowledge. The master polls the data line during this clock pulse and sets the Data Acknowledge bit (DNACK) in the Status Register if the slave does not acknowledge the data byte.
AT32UC3A3 1. Wait until RHR is empty, stretching low period of TWCK. SR.RXRDY indicates the state of RHR. Software or the Peripheral DMA Controller must read any data byte present in RHR. 2. Release TWCK generating a clock that the slave uses to transmit a data byte. 3. Place the received data byte in RHR, set RXRDY. 4. If NBYTES=0, generate a NAK after the data byte, otherwise generate an ACK. 5. Decrement NBYTES 6. If (NBYTES==0) and STOP=1, transmit STOP condition.
AT32UC3A3 23.8.5 Using the Peripheral DMA Controller The use of the Peripheral DMA Controller significantly reduces the CPU load. The user can set up ring buffers for the Peripheral DMA Controller, containing data to transmit or free buffer space to place received data. To assure correct behavior, respect the following programming sequences: 23.8.5.1 Data Transmit with the Peripheral DMA Controller 1. Initialize the transmit Peripheral DMA Controller (memory pointers, size, etc.). 2.
AT32UC3A3 Figure 23-10. User Sends Data While the Bus is Busy TWCK START sent by the TWI STOP sent by the master DATA sent by a master TWD DATA sent by the TWI Bus is busy Bus is free Transfer is kept TWI DATA transfer A transfer is programmed (DADR + W + START + Write THR) Bus is considered as free Transfer is initiated Figure 23-11.
AT32UC3A3 As for single data transfers, the TXRDY and RXRDY bits in the Status Register indicates when data to transmit can be written to THR, or when received data can be read from RHR. Transfer of data to THR and from RHR can also be done automatically by DMA, see Section 23.8.5 23.8.7.1 Write Followed by Write Consider the following transfer: START, DADR+W, DATA+A, DATA+A, REPSTART, DADR+W, DATA+A, DATA+A, STOP. To generate this transfer: 1. Write CMDR with START=1, STOP=0, DADR, NBYTES=2 and READ=0. 2.
AT32UC3A3 Figure 23-12. Combining a Write and Read Transfer THR DATA0 DATA1 RHR TWD DATA2 S DADR W A DATA0 A DATA1 NA Sr R DADR A DATA2 A DATA3 DATA3 A P SR.IDLE 1 TXRDY RXRDY To generate this transfer: 1. Write CMDR with START=1, STOP=0, DADR, NBYTES=2 and READ=0. 2. Write NCMDR with START=1, STOP=1, DADR, NBYTES=2 and READ=1. 3. Wait until SR.TXRDY==1, then write first data byte to transfer to THR. 4. Wait until SR.TXRDY==1, then write second data byte to transfer to THR. 5.
AT32UC3A3 23.8.8 Ten Bit Addressing Writing a one to CMDR.TENBIT enables 10-bit addressing in hardware. Performing transfers with 10-bit addressing is similar to transfers with 7-bit addresses, except that bits 9:7 of CMDR.SADR must be written appropriately. In Figure 23-14 and Figure 23-15, the grey boxes represent signals driven by the master, the white boxes are driven by the slave. 23.8.8.1 Master Transmitter To perform a master transmitter transfer: 1.
AT32UC3A3 23.8.9.1 Packet Error Checking Each SMBus transfer can optionally end with a CRC byte, called the PEC byte. Writing a one to CMDR.PECEN enables automatic PEC handling in the current transfer. Transfers with and without PEC can freely be intermixed in the same system, since some slaves may not support PEC. The PEC LFSR is always updated on every bit transmitted or received, so that PEC handling on combined transfers will be correct.
AT32UC3A3 23.8.10 Identifying Bus Events This chapter lists the different bus events, and how they affect bits in the TWIM registers. This is intended to help writing drivers for the TWIM. Table 23-5. Bus Events Event Effect Master transmitter has sent a data byte SR.THR is cleared. Master receiver has received a data byte SR.RHR is set. Start+Sadr sent, no ack received from slave SR.ANAK is set. SR.CCOMP not set. CMDR.VALID remains set. STOP automatically transmitted on bus.
AT32UC3A3 23.9 User Interface Table 23-6.
AT32UC3A3 23.9.1 Name: Control Register CR Access Type: Write-only Offset: 0x00 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - STOP 7 6 5 4 3 2 1 0 SWRST - SMDIS SMEN - - MDIS MEN • STOP: Stop the Current Transfer Writing a one to this bit terminates the current transfer, sending a STOP condition after the shifter has become idle.
AT32UC3A3 23.9.2 Name: Clock Waveform Generator Register CWGR Access Type: Read/Write Offset: 0x04 Reset Value: 0x00000000 31 30 - 23 29 28 27 26 EXP 22 21 25 24 DATA 20 19 18 17 16 11 10 9 8 3 2 1 0 STASTO 15 14 13 12 HIGH 7 6 5 4 LOW • EXP: Clock Prescaler Used to specify how to prescale the TWCK clock.
AT32UC3A3 23.9.3 Name: SMBus Timing Register SMBTR Access Type: Read/Write Offset: 0x08 Reset Value: 0x00000000 31 30 29 28 EXP 23 22 21 20 27 26 25 24 - - - - 19 18 17 16 11 10 9 8 3 2 1 0 THMAX 15 14 13 12 TLOWM 7 6 5 4 TLOWS • EXP: SMBus Timeout Clock Prescaler Used to specify how to prescale the TIM and TLOWM counters in SMBTR.
AT32UC3A3 23.9.4 Name: Command Register CMDR Access Type: Read/Write Offset: 0x0C Reset Value: 0x00000000 31 30 - 23 29 28 - 22 21 20 27 26 25 24 - - ACKLAST PECEN 19 18 17 16 10 9 8 NBYTES 15 14 13 12 11 VALID STOP START REPSAME TENBIT 7 6 5 4 3 SADR[6:0] SADR[9:7] 2 1 0 READ • ACKLAST: ACK Last Master RX Byte 0: Causes the last byte in master receive mode (when NBYTES has reached 0) to be NACKed.
AT32UC3A3 Write this bit to one if the command in CMDR performs a repeated start to the same slave address as addressed in the previous transfer in order to enter master receiver mode. Write this bit to zero otherwise. • TENBIT: Ten Bit Addressing Mode 0: Use 7-bit addressing mode. 1: Use 10-bit addressing mode. Must not be used when the TWIM is in SMBus mode. • SADR: Slave Address Address of the slave involved in the transfer. Bits 9-7 are don’t care if 7-bit addressing is used.
AT32UC3A3 23.9.5 Name: Next Command Register NCMDR Access Type: Read/Write Offset: 0x10 Reset Value: 0x00000000 31 30 - 29 28 - 23 22 21 20 27 26 25 24 - - ACKLAST PECEN 19 18 17 16 10 9 8 NBYTES 15 14 13 12 11 VALID STOP START REPSAME TENBIT 7 6 5 4 3 SADR[6:0] SADR[9:7] 2 1 0 READ This register is identical to CMDR. When the VALID bit in CMDR becomes 0, the content of NCMDR is copied into CMDR, clearing the VALID bit in NCMDR.
AT32UC3A3 23.9.6 Name: Receive Holding Register RHR Access Type: Read-only Offset: 0x14 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 RXDATA • RXDATA: Received Data When the RXRDY bit in the Status Register (SR) is one, this field contains a byte received from the TWI bus.
AT32UC3A3 23.9.7 Name: Transmit Holding Register THR Access Type: Write-only Offset: 0x18 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 TXDATA • TXDATA: Data to Transmit Write data to be transferred on the TWI bus here.
AT32UC3A3 23.9.8 Name: Status Register SR Access Type: Read-only Offset: 0x1C Reset Value: 0x00000002 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - MENB 15 14 13 12 11 10 9 8 - STOP PECERR TOUT SMBALERT ARBLST DNAK ANAK 7 6 5 4 3 2 1 0 - - BUSFREE IDLE CCOMP CRDY TXRDY RXRDY • MENB: Master Interface Enable 0: Master interface is disabled. 1: Master interface is enabled.
AT32UC3A3 • IDLE: Master Interface is Idle This bit is one when no command is in progress, and no command waiting to be issued. Otherwise, this bit is cleared. • CCOMP: Command Complete This bit is one when the current command has completed successfully. This bit is zero if the command failed due to conditions such as a NAK receved from slave. This bit is cleared by writing 1 to the corresponding bit in the Status Clear Register (SCR).
AT32UC3A3 23.9.9 Name: Interrupt Enable Register IER Access Type: Write-only Offset: 0x20 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - PECERR TOUT SMBALERT ARBLST DNAK ANAK 7 6 5 4 3 2 1 0 - - BUSFREE IDLE CCOMP CRDY TXRDY RXRDY Writing a zero to a bit in this register has no effect.
AT32UC3A3 23.9.10 Name: Interrupt Disable Register IDR Access Type: Write-only Offset: 0x24 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - PECERR TOUT SMBALERT ARBLST DNAK ANAK 7 6 5 4 3 2 1 0 - - BUSFREE IDLE CCOMP CRDY TXRDY RXRDY Writing a zero to a bit in this register has no effect.
AT32UC3A3 23.9.11 Name: Interrupt Mask Register IMR Access Type: Read-only Offset: 0x28 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - PECERR TOUT SMBALERT ARBLST DNAK ANAK 7 6 5 4 3 2 1 0 - - BUSFREE IDLE CCOMP CRDY TXRDY RXRDY 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled.
AT32UC3A3 23.9.12 Name: Status Clear Register SCR Access Type : Write-only Offset: 0x2C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - STOP PECERR TOUT SMBALERT ARBLST DNAK ANAK 7 6 5 4 3 2 1 0 - - - - CCOMP - - - Writing a zero to a bit in this register has no effect.
AT32UC3A3 23.9.
AT32UC3A3 23.9.14 Name: Version Register (VR) VR Access Type: Read-only Offset: 0x34 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION [11:8] 3 2 1 0 VERSION [7:0] • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated.
AT32UC3A3 23.10 Module Configuration The specific configuration for each TWIM instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks according to the table in the Power Manager section. Table 23-7. Module Clock Name Module name Clock name TWIM0 CLK_TWIM0 TWIM1 CLK_TWIM1 Table 23-8.
AT32UC3A3 24. Synchronous Serial Controller (SSC) Rev: 3.2.0.2 24.
AT32UC3A3 24.3 Block Diagram Figure 24-1. SSC Block Diagram High Speed Bus Peripheral Bus Bridge Peripheral DMA Controller Peripheral Bus TX_FRAME_SYNC TX_CLOCK TX_DATA Power CLK_SSC Manager SSC Interface I/O Controller RX_FRAME_SYNC RX_CLOCK Interrupt Control RX_DATA SSC Interrupt 24.4 Application Block Diagram Figure 24-2.
AT32UC3A3 24.5 I/O Lines Description Table 24-1. 24.6 I/O Lines Description Pin Name Pin Description Type RX_FRAME_SYNC Receiver Frame Synchro Input/Output RX_CLOCK Receiver Clock Input/Output RX_DATA Receiver Data Input TX_FRAME_SYNC Transmitter Frame Synchro Input/Output TX_CLOCK Transmitter Clock Input/Output TX_DATA Transmitter Data Output Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 24.6.
AT32UC3A3 Figure 24-3.
AT32UC3A3 24.7.1.1 Clock divider Figure 24-4. Divided Clock Block Diagram Clock Divider CMR CLK_SSC /2 12-bit Counter Divided Clock The peripheral clock divider is determined by the 12-bit Clock Divider field (its maximal value is 4095) in the Clock Mode Register (CMR.DIV), allowing a peripheral clock division by up to 8190. The divided clock is provided to both the receiver and transmitter. When this field is written to zero, the clock divider is not used and remains inactive. When CMR.
AT32UC3A3 be inverted independently by writing a one to the Transmit Clock Inversion bit in TCMR (TCMR.CKI). The transmitter can also drive the TX_CLOCK pin continuously or be limited to the actual data transfer, depending on the Transmit Clock Output Mode Selection field in the TCMR register (TCMR.CKO). The TCMR.CKI bit has no effect on the clock outputs. Writing 0b10 to the TCMR.CKS field to select TX_CLOCK pin and 0b001 to the TCMR.
AT32UC3A3 Figure 24-7. Receiver Clock Management RX_CLOCK Tri-state Controller MUX Clock Output Transmitter Clock Divider Clock Data Transfer CKO CKS 24.7.1.4 INV MUX Tri-state Controller CKI CKG Receiver Clock Serial clock ratio considerations The transmitter and the receiver can be programmed to operate with the clock signals provided on either the TX_CLOCK or RX_CLOCK pins. This allows the SSC to support many slave-mode data transfers.
AT32UC3A3 Figure 24-8. Transmitter Block Diagram CR.TXEN SR.TXEN CR.TXDIS TFMR.DATDEF 1 TX_FRAME_SYNC RX_FRAME_SYNC Transmitter Clock Start Selector TX_DATA 0 TFMR.MSBF Transmit Shift Register 0 TFMR.FSDEN TCMR.STTDLY TFMR.DATLEN 24.7.3 TCMR.STTDLY TFMR.FSDEN TFMR.DATNB THR 1 TSHR TFMR.FSLEN Receiver Operations A received frame is triggered by a start event and can be followed by synchronization data before data transmission. The start event is configured by writing to the RCMR register.
AT32UC3A3 Figure 24-9. Receiver Block Diagram RX_CLO C K T ri-sta te C o n tro lle r MUX C lo ck O u tp u t T ra n sm itte r C lo ck D ivid e r C lo ck D a ta T ra n sfe r CKO CKS 24.7.4 IN V MUX T ri-sta te C o n tro lle r CKI CKG R e ce ive r C lo ck Start The transmitter and receiver can both be programmed to start their operations when an event occurs, respectively in the Transmit Start Selection field of the TCMR register (TCMR.
AT32UC3A3 Figure 24-10.
AT32UC3A3 24.7.5 Frame Sync The transmitter and receiver frame synchro pins, TX_FRAME_SYNC and RX_FRAME_SYNC, can be programmed to generate different kinds of frame synchronization signals. The RFMR.FSOS and TFMR.FSOS fields are used to select the required waveform. • Programmable low or high levels during data transfer are supported. • Programmable high levels before the start of data transfers or toggling are also supported.
AT32UC3A3 and Transmit Sync bits in the SR register (SR.RXSYN and SR.TXSYN) on frame synchro edge detection (signals RX_FRAME_SYNC/TX_FRAME_SYNC). 24.7.6 Receive Compare Modes Figure 24-12. Receive Compare Modes RX_CLOCK RX_DATA (Input) CMP0 CMP1 CMP2 Ignored CMP3 B1 B0 B2 Start {FSLENHI,FSLEN} Up to 256 Bits (4 in This Example) 24.7.6.1 24.7.7 STTDLY DATLEN Compare functions Compare 0 can be one start event of the receiver.
AT32UC3A3 Table 24-3. Data Framing Format Registers Transmitter Receiver Bit/Field Length Comment TFMR RFMR DATNB Up to 16 Number of words transmitted in frame TFMR RFMR DATLEN Up to 32 Size of word TFMR RFMR {FSLENHI,FSLEN} Up to 256 Size of Synchro data register TFMR RFMR MSBF Most significant bit first TFMR FSDEN Enable send TSHR TFMR DATDEF Data default value ended Figure 24-13.
AT32UC3A3 Figure 24-15. Receive Frame Format in Continuous Mode Start = Enable Receiver RX_DATA Note: 24.7.8 Data Data To RHR To RHR DATLEN DATLEN STTDLY is written to zero. Loop Mode The receiver can be programmed to receive transmissions from the transmitter. This is done by writing a one to the Loop Mode bit in RFMR register (RFMR.LOOP). In this case, RX_DATA is connected to TX_DATA, RX_FRAME_SYNC is connected to TX_FRAME_SYNC and RX_CLOCK is connected to TX_CLOCK. 24.7.
AT32UC3A3 24.8 SSC Application Examples The SSC can support several serial communication modes used in audio or high speed serial links. Some standard applications are shown in the following figures. All serial link applications supported by the SSC are not listed here. Figure 24-17.
AT32UC3A3 Figure 24-19.
AT32UC3A3 24.9 User Interface Table 24-4.
AT32UC3A3 24.9.1 Name: Control Register CR Access Type: Write-only Offset: 0x00 Reset value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 SWRST - - - - - TXDIS TXEN 7 6 5 4 3 2 1 0 - - - - - - RXDIS RXEN • SWRST: Software Reset 1: Writing a one to this bit will perform a software reset. This software reset has priority on any other bit in CR.
AT32UC3A3 24.9.2 Name: Clock Mode Register CMR Access Type: Read/Write Offset: 0x04 Reset value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - 7 6 5 4 1 0 DIV[11:8] 3 2 DIV[7:0] • DIV[11:0]: Clock Divider The divided clock equals the CLK_SSC divided by two times DIV. The maximum bit rate is CLK_SSC/2. The minimum bit rate is CLK_SSC/(2 x 4095) = CLK_SSC/8190.
AT32UC3A3 24.9.3 Name: Receive Clock Mode Register RCMR Access Type: Read/Write Offset: 0x10 Reset value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 1 0 PERIOD 23 22 21 20 STTDLY 15 14 13 12 - - - STOP 7 6 5 4 CKG CKI START 3 CKO 2 CKS • PERIOD: Receive Period Divider Selection This field selects the divider to apply to the selected receive clock in order to generate a periodic Frame Sync Signal. If equal to zero, no signal is generated.
AT32UC3A3 • START: Receive Start Selection START Receive Start 0 Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
AT32UC3A3 24.9.4 Name: Receive Frame Mode Register RFMR Access Type: Read/Write Offset: 0x14 Reset value: 0x00000000 31 30 29 28 FSLENHI 23 22 - 21 20 27 26 25 24 - - - FSEDGE 19 18 17 16 9 8 1 0 FSOS FSLEN 15 14 13 12 - - - - 7 6 5 4 MSBF - LOOP 11 10 DATNB 3 2 DATLEN • FSLENHI: Receive Frame Sync Length High Part The four MSB of the FSLEN field. • FSEDGE: Receive Frame Sync Edge Detection Determines which edge on Frame Sync will generate the SR.
AT32UC3A3 • DATNB: Data Number per Frame This field defines the number of data words to be received after each transfer start, which is equal to (DATNB + 1). • MSBF: Most Significant Bit First 1: The most significant bit of the data register is sampled first in the bit stream. 0: The lowest significant bit of the data register is sampled first in the bit stream. • LOOP: Loop Mode 1: RX_DATA is driven by TX_DATA, RX_FRAME_SYNC is driven by TX_FRAME_SYNC and TX_CLOCK drives RX_CLOCK. 0: Normal operating mode.
AT32UC3A3 24.9.5 Name: Transmit Clock Mode Register TCMR Access Type: Read/Write Offset: 0x18 Reset value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 1 0 PERIOD 23 22 21 20 STTDLY 15 14 13 12 - - - - 7 6 5 4 CKG CKI START 3 CKO 2 CKS • PERIOD: Transmit Period Divider Selection This field selects the divider to apply to the selected transmit clock in order to generate a periodic Frame Sync Signal. If equal to zero, no signal is generated.
AT32UC3A3 • CKG: Transmit Clock Gating Selection CKG Transmit Clock Gating 0 None, continuous clock 1 Transmit Clock enabled only if TX_FRAME_SYNC is low 2 Transmit Clock enabled only if TX_FRAME_SYNC is high 3 Reserved • CKI: Transmit Clock Inversion CKI affects only the Transmit Clock and not the output clock signal. 1: The data outputs (Data and Frame Sync signals) are shifted out on transmit clock rising edge. The Frame sync signal input is sampled on transmit clock falling edge.
AT32UC3A3 24.9.6 Name: Transmit Frame Mode Register TFMR Access Type: Read/Write Offset: 0x1C Reset value: 0x00000000 31 30 29 28 FSLENHI 23 22 21 FSDEN 20 27 26 25 24 - - - FSEDGE 19 18 17 16 9 8 1 0 FSOS FSLEN 15 14 13 12 - - - - 7 6 5 4 MSBF - DATDEF 11 10 DATNB 3 2 DATLEN • FSLENHI: Transmit Frame Sync Length High Part The four MSB of the FSLEN field.
AT32UC3A3 • • • • The pulse length is equal to ({FSLENHI,FSLEN} + 1) transmit clock periods, i.e., the pulse length can range from 1 to 256 transmit clock periods. If {FSLENHI,FSLEN} is zero, the Transmit Frame Sync signal is generated during one transmit clock period. DATNB: Data Number per Frame This field defines the number of data words to be transferred after each transfer start, which is equal to (DATNB + 1).
AT32UC3A3 24.9.7 Name: Receive Holding Register RHR Access Type: Read-only Offset: 0x20 Reset value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RDAT[31:24] 23 22 21 20 RDAT[23:16] 15 14 13 12 RDAT[15:8] 7 6 5 4 RDAT[7:0] • RDAT: Receive Data Right aligned regardless of the number of data bits defined by the RFMR.DATLEN field.
AT32UC3A3 24.9.8 Name: Transmit Holding Register THR Access Type: Write-only Offset: 0x24 Reset value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 TDAT[31:24] 23 22 21 20 TDAT[23:16] 15 14 13 12 TDAT[15:8] 7 6 5 4 TDAT[7:0] • TDAT: Transmit Data Right aligned regardless of the number of data bits defined by the TFMR.DATLEN field.
AT32UC3A3 24.9.
AT32UC3A3 24.9.
AT32UC3A3 24.9.
AT32UC3A3 24.9.
AT32UC3A3 24.9.13 Name: Status Register SR Access Type: Read-only Offset: 0x40 Reset value: 0x000000CC 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - RXEN TXEN 15 14 13 12 11 10 9 8 - - - - RXSYN TXSYN CP1 CP0 7 6 5 4 3 2 1 0 - - OVRUN RXRDY - - TXEMPTY TXRDY • RXEN: Receive Enable This bit is set when the CR.RXEN bit is written to one. This bit is cleared when no data are being processed and the CR.
AT32UC3A3 • TXRDY: Transmit Ready This bit is set when the THR register is empty. This bit is cleared when data has been loaded in the THR register and is waiting to be loaded in the TSR register.
AT32UC3A3 24.9.14 Name: Interrupt Enable Register IER Access Type: Write-only Offset: 0x44 Reset value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - RXSYN TXSYN CP1 CP0 7 6 5 4 3 2 1 0 – – OVRUN RXRDY – – TXEMPTY TXRDY Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR.
AT32UC3A3 24.9.15 Name: Interrupt Disable Register IDR Access Type: Write-only Offset: 0x48 Reset value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - RXSYN TXSYN CP1 CP0 7 6 5 4 3 2 1 0 – – OVRUN RXRDY – – TXEMPTY TXRDY Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR.
AT32UC3A3 24.9.16 Name: Interrupt Mask Register IMR Access Type: Read-only Offset: 0x4C Reset value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - RXSYN TXSYN CP1 CP0 7 6 5 4 3 2 1 0 – – OVRUN RXRDY – – TXEMPTY TXRDY 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled.
AT32UC3A3 25. Universal Synchronous Asynchronous Receiver Transmitter (USART) Rev: 4.2.0.6 25.1 Features • Configurable baud rate generator • 5- to 9-bit full-duplex, synchronous and asynchronous, serial communication • • • • • • • 25.2 – 1, 1.
AT32UC3A3 frame lengths with the time-out feature. The USART supports several operating modes, providing an interface to RS485, LIN, and SPI buses, with ISO7816 T=0 and T=1 smart card slots, infrared transceivers, and modem port connections. Communication with slow and remote devices is eased by the timeguard. Duplex multidrop communication is supported by address and data differentiation through the parity bit.
AT32UC3A3 Table 25-1. 25.4 SPI Operating Mode PIN USART SPI Slave SPI Master RXD RXD MOSI MISO TXD TXD MISO MOSI RTS RTS – CS CTS CTS CS – I/O Lines Description Table 25-2.
AT32UC3A3 25.5.2 Clocks The clock for the USART bus interface (CLK_USART) is generated by the Power Manager. This clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the USART before disabling the clock, to avoid freezing the USART in an undefined state. 25.5.3 Interrupts The USART interrupt request line is connected to the interrupt controller. Using the USART interrupt requires the interrupt controller to be programmed first.
AT32UC3A3 25.6 25.6.1 Functional Description USART Operating Modes The USART can operate in several modes: • Normal • RS485, described in Section 25.6.5 ”RS485 Mode” on page 560 • Hardware handshaking, described in Section 25.6.6 ”Hardware Handshaking” on page 561 • Modem, described in Section 25.6.7 ”Modem Mode” on page 562 • ISO7816, described in Section 25.6.8 ”ISO7816 Mode” on page 563 • IrDA, described in Section 25.6.9 ”IrDA Mode” on page 566 • LIN Master, described in Section 25.6.
AT32UC3A3 4. Check that CSR.TXRDY and/or CSR.RXRDY is one before writing to THR and/or reading from RHR respectively 25.6.2.1 Receiver and Transmitter Control After a reset, the transceiver is disabled. The receiver/transmitter is enabled by writing a one to the Receiver Enable/Transmitter Enable bit in the Control Register (CR.RXEN/CR.TXEN) respectively. They may be enabled together and can be configured both before and after they have been enabled.
AT32UC3A3 Figure 25-3. Transmitter Status Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Start D0 Bit Bit Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Write THR TXRDY TXEMPTY 25.6.2.3 Asynchronous Receiver If the USART is configured in an asynchronous operating mode (MR.SYNC is zero), the receiver will oversample the RXD input line by either 8 or 16 times the Baud Rate Clock, as selected by the Oversampling Mode bit (MR.OVER).
AT32UC3A3 Figure 25-5. Asynchronous Mode Character Reception Example: 8-bit, Parity Enabled Baud Rate Clock RXD Start Detection 16 16 16 16 16 16 16 16 16 16 samples samples samples samples samples samples samples samples samples samples D0 25.6.2.4 D1 D2 D3 D4 D5 D6 D7 Parity Bit Stop Bit Synchronous Receiver In synchronous mode (MR.SYNC is one), the receiver samples the RXD signal on each rising edge of the Baud Rate Clock, as illustrated in Figure 25-6.
AT32UC3A3 Interrupt Mask Register (IMR.RXRDY) is set. If CSR.RXRDY is already set, RHR will be overwritten and the Overrun Error bit (CSR.OVRE) is set. An interrupt request is generated if the Overrun Error bit in IMR is set. Reading RHR will clear CSR.RXRDY, and writing a one to the Reset Status bit in the Control Register (CR.RSTSTA) will clear CSR.OVRE. Refer to Figure 257. 25.6.3 25.6.3.1 Other Considerations Parity The USART supports five parity modes, selected by MR.
AT32UC3A3 25.6.3.2 Multidrop Mode If MR.PAR is either 0x6 or 0x7, the USART runs in Multidrop mode. This mode differentiates data and address characters. Data has the parity bit zero and addresses have a one. By writing a one to the Send Address bit (CR.SENDA) the user will cause the next character written to THR to be transmitted as an address. Receiving a character with a one as parity bit will report parity error by setting CSR.PARE.
AT32UC3A3 25.6.3.4 Receiver Time-out The Time-out Value field in the Receiver Time-out Register (RTOR.TO) enables handling of variable-length frames by detection of selectable idle durations on the RXD line. The value written to TO is loaded to a decremental counter, and unless it is zero, a time-out will occur when the amount of inactive bit periods matches the initial counter value. If a time-out has not occurred, the counter will reload and restart every time a new character arrives.
AT32UC3A3 25.6.3.5 Framing Error The receiver is capable of detecting framing errors. A framing error has occurred if a stop bit reads as zero. This can occur if the transmitter and receiver are not synchronized. A framing error is reported by CSR.FRAME as soon as the error is detected, at the middle of the stop bit. An interrupt request is generated if the Framing Error bit in the Interrupt Mask Register (IMR.FRAME) is set. CSR.FRAME is cleared by writing a one to CR.RSTSTA. Figure 25-11.
AT32UC3A3 25.6.3.7 25.6.4 Receive Break A break condition is assumed when incoming data, parity, and stop bits are zero. This corresponds to a framing error, but CSR.FRAME will remain zero while the Break Received/End of Break bit (CSR.RXBRK) is set. An interrupt request is generated if the Breadk Received/End of Break bit in the Interrupt Mask Register is set (IMR.RXBRK). Writing a one to CR.RSTSTA will clear CSR.RXBRK. An end of break will also set CSR.
AT32UC3A3 This gives a maximum baud rate of CLK_USART divided by 8, assuming that CLK_USART is the fastest clock available, and that MR.OVER is one. 25.6.4.2 Table 25-7. Baud Rate Calculation Example Table 25-7 shows calculations based on the CD field to obtain 38400 baud from different source clock frequencies. This table also shows the actual resulting baud rate and error.
AT32UC3A3 the Fractional Part field in BRGR (BRGR.FP), and is activated by giving it a non-zero value. The resolution is one eighth of CD. The resulting baud rate is calculated using the following formula: SelectedClock BaudRate = ------------------------------------------------------------------⎛ 8 ( 2 – OVER ) ⎛ CD + FP -------⎞ ⎞ ⎝ ⎝ 8 ⎠⎠ The modified architecture is shown in Figure 25-14. Figure 25-14.
AT32UC3A3 Figure 25-15. Typical Connection to a RS485 Bus USART RXD Differential Bus TXD RTS If a timeguard has been configured the RTS pin will remain high for the duration specified in TG, as shown in Figure 25-16. Figure 25-16. Example of RTS Drive with Timeguard Enabled TG = 4 Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Write THR TXRDY TXEMPTY RTS 25.6.
AT32UC3A3 Writing 0x2 to the MR.MODE field configures the USART to operate in hardware handshaking mode. The receiver will drive its RTS pin high when disabled or when the Reception Buffer Full bit (CSR.RXBUFF) is set by the Buffer Full signal from the Peripheral DMA controller. If the receiver RTS pin is high, the transmitter CTS pin will also be high and only the active character transmissions will be completed.
AT32UC3A3 Table 25-8. Circuit References USART Pin V.24 CCITT Direction DSR 6 107 From terminal to modem DCD 8 109 From terminal to modem RI 22 125 From terminal to modem The DTR pin is controlled by the DTR enable and disable bits in CR (CR.DTREN and CR.DTRDIS). Writing a one to CR.DTRDIS drives DTR high, and writing a one to CR.DTREN drives DTR low. The RTS pin is controlled automatically. Detected level changes are reported by the respective Input Change bits in CSR (CSR.RIIC, CSR.
AT32UC3A3 • B is the bit rate • Di is the bit-rate adjustment factor • Fi is the clock frequency division factor • f is the ISO7816 clock frequency (Hz) Di is a binary value encoded on a 4-bit field, named DI, as represented in Table 25-9. Table 25-9. Binary and Decimal Values for Di DI field 0001 0010 0011 0100 0101 0110 1000 1001 1 2 4 8 16 32 12 20 Di (decimal) Fi is a binary value encoded on a 4-bit field, named FI, as represented in Table 25-10. Table 25-10.
AT32UC3A3 Figure 25-21. Elementary Time Unit (ETU) FI_DI_RATIO ISO7816 Clock Cycles ISO7816 Clock on CLK ISO7816 I/O Line on TXD 1 ETU 25.6.8.3 Protocol T=0 In T=0 protocol, a character is made up of one start bit, eight data bits, one parity bit, and a two bit period guard time. During the guard time, the line will be high if the receiver does not signal a parity error, as shown in Figure 25-22.
AT32UC3A3 25.6.8.7 Transmit Character Repetition The USART can be configured to automatically re-send a character if it receives a NACK. Writing a non-zero value to MR.MAX_ITERATION will enable and determine the number of consecutive re-transmissions. If the number of unsuccessful re-transmissions equals MAX_ITERATION, the iteration bit (CSR.ITER) is set. An interrupt request is generated if the ITER bit in the Interrupt Mask Register (IMR.ITER) is set. Writing a one to the Reset Iteration bit (CR.
AT32UC3A3 25.6.9.1 IrDA Modulation The RZI modulation scheme is used, where a zero is represented by a light pulse 3/16 of a bit period, and no pulse to represent a one. Some examples of signal pulse duration are shown in Table 25-12. Table 25-12. IrDA Pulse Duration Baud Rate Pulse Duration (3/16) 2.4 Kbit/s 78.13 µs 9.6 Kbit/s 19.53 µs 19.2 Kbit/s 9.77 µs 38.4 Kbit/s 4.88 µs 57.6 Kbit/s 3.26 µs 115.2 Kbit/s 1.63 µs Figure 25-25 shows an example of character transmission. Figure 25-25.
AT32UC3A3 Table 25-13. IrDA Baud Rate Error (Continued) Peripheral Clock 25.6.9.3 Baud Rate CD Baud Rate Error Pulse Time 3 686 400 38 400 6 0.00% 4.88 20 000 000 38 400 33 1.38% 4.88 32 768 000 38 400 53 0.63% 4.88 40 000 000 38 400 65 0.16% 4.88 3 686 400 19 200 12 0.00% 9.77 20 000 000 19 200 65 0.16% 9.77 32 768 000 19 200 107 0.31% 9.77 40 000 000 19 200 130 0.16% 9.77 3 686 400 9 600 24 0.00% 19.53 20 000 000 9 600 130 0.16% 19.
AT32UC3A3 25.6.10.1 Modes of Operation Changing LIN mode after initial configuration must be followed by a transceiver software reset in order to avoid unpredictable behavior. 25.6.10.2 Receiver and Transmitter Control See Section “25.6.2.1” on page 551. 25.6.10.3 Baud Rate Configuration The LIN nodes baud rate is configured in the Baud Rate Generator Register (BRGR), See Section “25.6.4.1” on page 558. 25.6.10.
AT32UC3A3 Figure 25-28. Header Reception Baud Rate Clock RXD Break Field 13 dominant bits (at 0) LINID Break Delimiter 1 recessive bit (at 1) Start 1 Bit 0 1 0 1 0 1 0 Synch Byte = 0x55 Stop Stop Start ID0 ID1 ID2 ID3 ID4 ID5 ID6 ID7 Bit Bit Bit US_LINIR Write US_CR With RSTSTA=1 See also ”Slave Node Configuration” on page 576. 25.6.10.7 Slave Node Synchronization Synchronization is only done by the slave.
AT32UC3A3 • The theoretical slave node clock frequency; nominal clock frequency (FNom) • The baud rate • The oversampling mode (OVER=0 => 16x, or OVER=1 => 8x) The following formula is used to calculate synchronization deviation, where FSLAVE is the real slave node clock frequency, and FTOL_UNSYNC is the difference between FNom and FSLAVE.
AT32UC3A3 enabled by default, and can be disabled by writing a one to the Parity Disable bit in the LIN Mode register (LINMR.PARDIS). • LINMR.PARDIS=0: During header transmission, the parity bits are computed and in the shift register they replace bits 6 and 7 from LINIR.IDCHR. During header reception, the parity bits are checked and can generate a LIN Identifier Parity Error (see Section 25.6.10.13). Bits 6 and 7 in LINIR.IDCHR read as zero when receiving. • LINMR.
AT32UC3A3 • LINMR.DLM=1: the response data length is defined by the Identifier (LINIR.IDCHR) bits according to the table below. Table 25-14. Response Data Length if DLM = 1 25.6.10.11 LINIR.IDCHR[5] LINIR.IDCHR[4] Response Data Length [bytes] 0 0 2 0 1 2 1 0 4 1 1 8 Checksum The last frame field is the checksum. It is configured by the Checksum Type (LINMR.CHKTYP), and the Checksum Disable (LINMR.CHKDIS) bits. CSR.TXRDY will not be set after the last THR data write if enabled.
AT32UC3A3 The minimum frame slot size is determined by TFrame_Maximum, and calculated below (all values in bit periods): • THeader_Nominal = 34 • TFrame_Maximum = 1.4 x (THeader_Nominal + TResponse_Nominal + 1) Note: The term “+1” leads to an integer result for TFrame_Max (LIN Specification 1.3) If the Checksum is sent (CHKDIS=0): • TResponse_Nominal = 10 x (NData + 1) • TFrame_Maximum = 1.
AT32UC3A3 • Write a one to CR.TXEN and CR.RXEN to enable both transmitter and receiver • Wait until CSR.TXRDY is one • Send the header by writing to LINIR.IDCHR The following procedure depends on the LINMR.NACT setting: • Case 1: LINMR.NACT is 0x0 (PUBLISH, the USART transmits the response) – Wait until CSR.TXRDY is one – Send a byte by writing to THR.TXCHR – Repeat the two previous steps until there is no more data to send – Wait until CSR.LINTC is one – Check for LIN errors • Case 2: LINMR.
AT32UC3A3 Figure 25-34. Master Node Configuration, LINMR.NACT is 0x1 (SUBSCRIBE) Frame slot = TFrame_Maximum Frame Data3 Header Break Synch Interframe space Response space Protected Identifier Response Data 1 Data N-1 Data N Checksum TXRDY FSDIS=1 FSDIS=0 RXRDY Write LINIR Read RHR Data 1 Data N-2 Data N-1 Data N LINTC Figure 25-35. Master Node Configuration, LINMR.
AT32UC3A3 The different LINMR.NACT settings result in the same procedure as for the master node, see page 574. Figure 25-36. Slave Node Configuration, LINMR.NACT is 0x0 (PUBLISH) Break Synch Protected Identifier Data 1 Data N-1 Data N Checksum Data N Checksum TXRDY RXRDY LINIDRX Read LINID Write THR Data 1 Data 2 Data 3 Data N LINTC Figure 25-37. Slave Node Configuration, LINMR.
AT32UC3A3 CSR.RXRDY bits to trigger one byte writes or reads. It always writes to THR, and it always reads RHR. 25.6.12.1 Master Node Configuration The Peripheral DMA Controller Mode bit (LINMR.PDCM) allows the user to select configuration: • LINMR.PDCM=0: LIN configuration must be written to LINMR, it is not stored in the write buffer. • LINMR.PDCM=1: LIN configuration is written by the Peripheral DMA Controller to THR, and is stored in the write buffer.
AT32UC3A3 Figure 25-40. Master Node with Peripheral DMA Controller (LINMR.PDCM=1) WRITE BUFFER WRITE BUFFER NACT PARDIS CHKDIS CHKTYP DLM FSDIS NACT PARDIS CHKDIS CHKTYP DLM FSDIS DLC DLC Peripheral bus NODE ACTION = PUBLISH Peripheral bus IDENTIFIER IDENTIFIER USART LIN CONTROLLER Peripheral DMA Controller READ BUFFER Peripheral DMA Controller NODE ACTION = SUBSCRIBE RXRDY USART LIN CONTROLLER RXRDY DATA 0 DATA 0 | | | | TXRDY | | | | DATA N DATA N 25.6.12.
AT32UC3A3 According to LIN 1.3, the wakeup request should be generated with the character 0x80 in order to impose eight successive dominant bits. According to LIN 2.0, the wakeup request is issued by forcing the bus into the dominant state for 250µs to 5ms. Sending the character 0xF0 does this, regardless of baud rate. • Baud rate max = 20 kbit/s -> one bit period = 50µs -> five bit periods = 250µs • Baud rate min = 1 kbit/s -> one bit period = 1ms -> five bit periods = 5ms 25.6.
AT32UC3A3 25.6.15.2 Baud Rate The baud rate generator operates as described in ”Baud Rate in Synchronous and SPI Mode” on page 560, with the following requirements: In SPI Master Mode: • External clock CLK must not be selected as clock (the Clock Selection field (MR.USCLKS) must not equal 0x3). • The USART must drive the CLK pin (MR.CLKO must be one). • The BRGR.CD field must be at least 0x4. • If the internal divided clock, CLK_USART/DIV, is selected (MR.USCLKS is one), the value in BRGR.
AT32UC3A3 Figure 25-42. SPI Transfer Format (CPHA=1, 8 bits per transfer) CLK cycle (for reference) 2 1 5 4 3 7 6 8 C LK (C POL= 0) C LK (CPO L= 1) M O SI SPI M aster ->TXD SPI Slave ->RXD M ISO SPI M aster ->RXD SPI Slave ->TXD M SB M SB 6 5 4 3 2 6 5 4 3 2 1 LSB 1 LSB NSS SPI M aster ->RTS SPI Slave ->CTS Figure 25-43.
AT32UC3A3 In SPI slave mode, a low level on NSS for at least one bit period will allow the slave to initiate a transmission or reception. The Underrun Error bit (CSR.UNRE) is set if a character must be sent while THR is empty, and TXD will be high during character transmission, as if 0xFF was being sent. An interrupt request is generated if the Underrun Error bit in the Interrupt Mask Register (IMR.UNRE) is set.
AT32UC3A3 Figure 25-45. Preamble Patterns, Default Polarity Assumed Manchester encoded data Txd SFD DATA SFD DATA SFD DATA SFD DATA 8 bit width "ALL_ONE" Preamble Manchester encoded data Txd 8 bit width "ALL_ZERO" Preamble Manchester encoded data Txd 8 bit width "ZERO_ONE" Preamble Manchester encoded data Txd 8 bit width "ONE_ZERO" Preamble The Start Frame Delimiter Selector bit (MR.ONEBIT) configures the Manchester start bit pattern following the preamble. If MR.
AT32UC3A3 Figure 25-46. Start Frame Delimiter Preamble Length is set to 0 SFD Manchester encoded data DATA Txd One bit start frame delimiter SFD Manchester encoded data DATA Txd Command Sync start frame delimiter SFD Manchester encoded data DATA Txd Data Sync start frame delimiter Manchester Drift Compensation The Drift Compensation bit (MAN.DRIFT) enables a hardware drift compensation and recovery system that allows for sub-optimal clock drifts without further user intervention.
AT32UC3A3 The Manchester endec uses the same Start Frame Delimiter Selector (MR.ONEBIT) for both encoder and decoder. If ONEBIT is one, only a Manchester encoded zero will be accepted as a valid start frame delimiter. If ONEBIT is zero, a data or command sync pattern will be expected. The Received Sync bit in the Receive Holding Register (RHR.RXSYNH) will be zero if the last character received is a data sync, and a one if it is a command sync. Figure 25-48.
AT32UC3A3 Figure 25-50. Manchester Error Preamble Length is set to 4 Elementary character bit time SFD Manchester encoded data Txd Entering USART character area sampling points Preamble subpacket and Start Frame Delimiter were successfully decoded 25.6.16.3 Manchester Coding Error detected Radio Interface: Manchester Endec Application This section describes low data rate, full duplex, dual frequency, RF systems integrated with a Manchester endec, that support ASK and/or FSK modulation schemes.
AT32UC3A3 Figure 25-52. ASK Modulator Output 1 0 0 1 NRZ stream Manchester encoded data default polarity unipolar output Txd ASK Modulator Output Uptstream Frequency F0 Figure 25-53. FSK Modulator Output 1 0 0 1 NRZ stream Manchester encoded data default polarity unipolar output Txd FSK Modulator Output Uptstream Frequencies [F0, F0+offset] 25.6.
AT32UC3A3 Figure 25-55. Automatic Echo Mode Configuration RXD Receiver TXD Transmitter 25.6.17.3 Local Loopback Mode Local loopback mode connects the output of the transmitter directly to the input of the receiver, as shown in Figure 25-56. The TXD and RXD pins are not used. The RXD pin has no effect on the receiver and the TXD pin is continuously driven high, as in idle state. Figure 25-56. Local Loopback Mode Configuration RXD Receiver 1 Transmitter 25.6.17.
AT32UC3A3 7 PARE 6 FRAME 5 OVRE 4 – 3 – 2 RXBRK 1 TXRDY 0 RXRDY The USART has the following interrupt sources: • LINSNRE: LIN Slave Not Responding Error – A LIN Slave Not Responding Error has been detected • LINCE: LIN Checksum Error – A LIN Checksum Error has been detected • LINIPE: LIN Identifier Parity Error – A LIN Identifier Parity Error has been detected • LINISFE: LIN Inconsistent Sync Field Error – The USART is configured as a Slave node and a LIN Inconsistent Sync Field Error has been detec
AT32UC3A3 – There has been a time-out since the last Start Time-out command. • PARE: Parity Error – Either at least one parity error has been detected, or the parity bit is a one in multidrop mode, since the last RSTSTA. • FRAME: Framing Error – At least one stop bit has been found as low since the last RSTSTA. • OVRE: Overrun Error – At least one overrun error has occurred since the last RSTSTA. • RXBRK: Break Received/End of Break – Break received or End of Break detected since the last RSTSTA.
AT32UC3A3 • ”Manchester Configuration Register” on page 614 592 32072H–AVR32–10/2012
AT32UC3A3 25.7 User Interface Table 25-17.
AT32UC3A3 25.7.1 Name: Control Register CR Access Type: Write-only Offset: 0x00 Reset Value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 LINWKUP 20 LINABT 19 RTSDIS/RCS 18 RTSEN/FCS 17 DTRDIS 16 DTREN 15 RETTO 14 RSTNACK 13 RSTIT 12 SENDA 11 STTTO 10 STPBRK 9 STTBRK 8 RSTSTA 7 TXDIS 6 TXEN 5 RXDIS 4 RXEN 3 RSTTX 2 RSTRX 1 – 0 – • LINWKUP: Send LIN Wakeup Signal Writing a zero to this bit has no effect.
AT32UC3A3 • SENDA: Send Address Writing a zero to this bit has no effect. Writing a one to this bit will in multidrop mode send the next character written to THR as an address. • STTTO: Start Time-out Writing a zero to this bit has no effect. Writing a one to this bit will abort any current time-out count down, and trigger a new count down when the next character has been received. CSR.TIMEOUT is also cleared. • STPBRK: Stop Break Writing a zero to this bit has no effect.
AT32UC3A3 25.7.2 Name: Mode Register MR Access Type: Read-write Offset: 0x04 Reset Value: 0x00000000 31 ONEBIT 30 MODSYNC 29 MAN 28 FILTER 27 – 26 25 MAX_ITERATION 24 23 – 22 VAR_SYNC 21 DSNACK 20 INACK 19 OVER 18 CLKO 17 MODE9 16 MSBF/CPOL 14 13 12 11 10 PAR 9 8 SYNC/CPHA 4 3 2 1 0 15 CHMODE 7 NBSTOP 6 CHRL 5 USCLKS MODE This register can only be written if write protection is disabled in the “Write Protect Mode Register” (WPMR.WPEN is zero).
AT32UC3A3 • MODE9: 9-bit Character Length 0: CHRL defines character length. 1: 9-bit character length. • MSBF/CPOL: Bit Order or SPI Clock Polarity If USART does not operate in SPI Mode: MSBF=0: Least Significant Bit is sent/received first. MSBF=1: Most Significant Bit is sent/received first. If USART operates in SPI Mode, CPOL is used with CPHA to produce the required clock/data relationship between devices. CPOL=0: The inactive state value of CLK is logic level zero.
AT32UC3A3 CPHA = 1: Data is captured on the leading edge of CLK and changed on the following edge of CLK. • CHRL: Character Length. Table 25-21. CHRL Character Length 0 0 5 bits 0 1 6 bits 1 0 7 bits 1 1 8 bits • USCLKS: Clock Selection Table 25-22. USCLKS Note: Selected Clock 0 0 CLK_USART 0 1 CLK_USART/DIV(1) 1 0 Reserved 1 1 CLK 1. The value of DIV is device dependent. Please refer to the Module Configuration section at the end of this chapter. • MODE Table 25-23.
AT32UC3A3 25.7.3 Name: Interrupt Enable Register IER Access Type: Write-only Offset: 0x08 Reset Value: 0x00000000 • • • • • • • • • • • • • • • • • • • • • • • 31 – 30 – 29 LINSNRE 28 LINCE 27 LINIPE 26 LINISFE 25 LINBE 24 MANEA 23 – 22 – 21 – 20 MANE 19 CTSIC 18 DCDIC 17 DSRIC 16 RIIC 15 LINTC 14 LINIR 13 NACK 12 RXBUFF 11 – 10 ITER/UNRE 9 TXEMPTY 8 TIMEOUT 7 PARE 6 FRAME 5 OVRE 4 – 3 – 2 RXBRK 1 TXRDY 0 RXRDY Writing a zero to a bit in this register has no effect.
AT32UC3A3 25.7.4 Name: Interrupt Disable Register IDR Access Type: Write-only Offset: 0x0C Reset Value: 0x00000000 • • • • • • • • • • • • • • • • • • • • • • • 31 – 30 – 29 LINSNRE 28 LINCE 27 LINIPE 26 LINISFE 25 LINBE 24 MANEA 23 – 22 – 21 – 20 MANE 19 CTSIC 18 DCDIC 17 DSRIC 16 RIIC 15 LINTC 14 LINIR 13 NACK 12 RXBUFF 11 – 10 ITER/UNRE 9 TXEMPTY 8 TIMEOUT 7 PARE 6 FRAME 5 OVRE 4 – 3 – 2 RXBRK 1 TXRDY 0 RXRDY Writing a zero to a bit in this register has no effect.
AT32UC3A3 25.7.5 Name: Interrupt Mask Register IMR Access Type: Read-only Offset: 0x10 Reset Value: 0x00000000 • • • • • • • • • • • • • • • • • • • • • • • 31 – 30 – 29 LINSNRE 28 LINCE 27 LINIPE 26 LINISFE 25 LINBE 24 MANEA 23 – 22 – 21 – 20 MANE 19 CTSIC 18 DCDIC 17 DSRIC 16 RIIC 15 LINTC 14 LINIR 13 NACK 12 RXBUFF 11 – 10 ITER/UNRE 9 TXEMPTY 8 TIMEOUT 7 PARE 6 FRAME 5 OVRE 4 – 3 – 2 RXBRK 1 TXRDY 0 RXRDY 0: The corresponding interrupt is disabled.
AT32UC3A3 25.7.
AT32UC3A3 1: DSR is high. • RI: Image of RI Input 0: RI is low. 1: RI is high. • CTSIC: Clear to Send Input Change Flag 0: No change has been detected on the CTS pin since the last CSR read. 1: At least one change has been detected on the CTS pin since the last CSR read. This bit is cleared when reading CSR. • DCDIC: Data Carrier Detect Input Change Flag 0: No change has been detected on the DCD pin since the last CSR read. 1: At least one change has been detected on the DCD pin since the last CSR read.
AT32UC3A3 • PARE: Parity Error 0: Either no parity error has been detected, or the parity bit is a zero in multidrop mode, since the last RSTSTA. 1: Either at least one parity error has been detected, or the parity bit is a one in multidrop mode, since the last RSTSTA. This bit is cleared by writing a one to CR.RSTSTA. • FRAME: Framing Error 0: No stop bit has been found as low since the last RSTSTA. 1: At least one stop bit has been found as low since the last RSTSTA.
AT32UC3A3 25.7.7 Name: Receiver Holding Register RHR Access Type: Read-only Offset: 0x18 Reset Value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 RXSYNH 14 – 13 – 12 – 11 – 10 – 9 – 8 RXCHR[8] 7 6 5 4 3 2 1 0 RXCHR[7:0] Reading this register will clear the CSR.RXRDY bit. • RXSYNH: Received Sync 0: Last character received is a data sync. 1: Last character received is a command sync.
AT32UC3A3 25.7.8 Name: Transmitter Holding Register THR Access Type: Write-only Offset: 0x1C Reset Value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 TXSYNH 14 – 13 – 12 – 11 – 10 – 9 – 8 TXCHR[8] 7 6 5 4 3 2 1 0 TXCHR[7:0] • TXSYNH: Sync Field to be transmitted 0: If MR.VARSYNC is one, the next character sent is encoded as data, and the start frame delimiter is a data sync. 1: If MR.
AT32UC3A3 25.7.9 Name: Baud Rate Generator Register BRGR Access Type: Read-write Offset: 0x20 Reset Value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 17 FP 16 15 14 13 12 11 10 9 8 3 2 1 0 CD[15:8] 7 6 5 4 CD[7:0] This register can only be written if write protection is disabled in the “Write Protect Mode Register” (WPMR.WPEN is zero). • FP: Fractional Part 0: Fractional divider is disabled.
AT32UC3A3 Table 25-26.
AT32UC3A3 25.7.10 Name: Receiver Time-out Register RTOR Access Type: Read-write Offset: 0x24 Reset Value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 TO[16] 15 14 13 12 11 10 9 8 3 2 1 0 TO[15:8] 7 6 5 4 TO[7:0] This register can only be written if write protection is disabled in the “Write Protect Mode Register” (WPMR.WPEN is zero). • TO: Time-out Value 0: The receiver Time-out is disabled.
AT32UC3A3 25.7.11 Name: Transmitter Timeguard Register TTGR Access Type: Read-write Offset: 0x28 Reset Value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 TG This register can only be written if write protection is disabled in the “Write Protect Mode Register” (WPMR.WPEN is zero). • TG: Timeguard Value 0: The transmitter Timeguard is disabled.
AT32UC3A3 25.7.12 Name: FI DI Ratio Register FIDI Access Type: Read-write Offset: 0x40 Reset Value: 0x00000174 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 9 FI_DI_RATIO[10:8] 8 7 6 5 4 3 FI_DI_RATIO[7:0] 2 1 0 This register can only be written if write protection is disabled in the “Write Protect Mode Register” (WPMR.WPEN is zero).
AT32UC3A3 25.7.13 Name: Number of Errors Register NER Access Type: Read-only Offset: 0x44 Reset Value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 NB_ERRORS • NB_ERRORS: Number of Errors Total number of errors that occurred during an ISO7816 transfer. This register is automatically cleared when read.
AT32UC3A3 25.7.14 Name: IrDA Filter Register IFR Access Type: Read-write Offset: 0x4C Reset Value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 IRDA_FILTER This register can only be written if write protection is disabled in the “Write Protect Mode Register” (WPMR.WPEN is zero). • IRDA_FILTER: IrDA Filter Configures the IrDA demodulator filter.
AT32UC3A3 25.7.15 Name: Manchester Configuration Register MAN Access Type: Read-write Offset: 0x50 Reset Value: 0x30011004 31 – 30 DRIFT 29 1 28 RX_MPOL 27 – 26 – 25 23 – 22 – 21 – 20 – 19 18 17 15 – 14 – 13 – 12 TX_MPOL 11 – 10 – 7 – 6 – 5 – 4 – 3 2 24 RX_PP 16 RX_PL 9 8 TX_PP 1 0 TX_PL This register can only be written if write protection is disabled in the “Write Protect Mode Register” (WPMR.WPEN is zero).
AT32UC3A3 • TX_PP: Transmitter Preamble Pattern Table 25-28. TX_PP Preamble Pattern default polarity assumed (TX_MPOL field not set) 0 0 ALL_ONE 0 1 ALL_ZERO 1 0 ZERO_ONE 1 1 ONE_ZERO • TX_PL: Transmitter Preamble Length 0: The transmitter preamble pattern generation is disabled. 1 - 15: The preamble length is TX_PL bit periods.
AT32UC3A3 25.7.16 Name: LIN Mode Register LINMR Access Type: Read-write Offset: 0x54 Reset Value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 PDCM 15 14 13 12 11 10 9 8 3 CHKDIS 2 PARDIS 1 DLC 7 WKUPTYP 6 FSDIS 5 DLM 4 CHKTYP 0 NACT • PDCM: Peripheral DMA Controller Mode 0: The LIN mode register is not written by the Peripheral DMA Controller.
AT32UC3A3 Table 25-29. 0 1 SUBSCRIBE: The USART receives the response. 1 0 IGNORE: The USART does not transmit and does not receive the response.
AT32UC3A3 25.7.17 Name: LIN Identifier Register LINIR Access Type: Read-write or Read-only Offset: 0x58 Reset Value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 IDCHR • IDCHR: Identifier Character If USART is in LIN master mode, the IDCHR field is read-write, and its value is the Identifier character to be transmitted.
AT32UC3A3 25.7.18 Write Protect Mode Register Register Name: WPMR Access Type: Read-write Offset: 0xE4 Reset Value: See Table 25-17 31 30 29 28 27 WPKEY[23:16] 26 25 24 23 22 21 20 19 18 17 16 11 10 9 8 3 - 2 - 1 - 0 WPEN WPKEY[15:8] 15 14 13 12 WPKEY[7:0] 7 - 6 - 5 - 4 - • WPKEY: Write Protect KEY Has to be written to 0x555341 (“USA” in ASCII) in order to successfully write WPEN. This bit always reads as zero. Writing the correct key to this field clears WPSR.
AT32UC3A3 25.7.19 Write Protect Status Register Register Name: WPSR Access Type: Read-only Offset: 0xE8 Reset Value: See Table 25-17 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 22 21 20 19 WPVSRC[15:8] 18 17 16 15 14 13 12 11 10 9 8 3 - 2 - 1 - 0 WPVS WPVSRC[7:0] 7 - 6 - 5 - 4 - • WPVSRC: Write Protect Violation Source If WPVS is one, this field indicates which write-protected register was unsuccessfully written to, either by address offset or code.
AT32UC3A3 25.7.20 Version Register Name: VERSION Access Type: Read-only Offset: 0xFC Reset Value: - 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 18 17 16 15 - 14 - 13 - 12 - 11 10 9 VERSION[11:8] 8 7 6 5 4 3 2 0 MFN 1 VERSION[7:0] • MFN Reserved. No functionality associated. • VERSION Version of the module. No functionality associated. 26.
AT32UC3A3 26.1 Module Configuration The specific configuration for each USART instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks according to the table in the System Bus Clock Connections section. Table 26-1.
AT32UC3A3 26.1.2 Register Reset Values Table 26-4.
AT32UC3A3 27. Hi-Speed USB Interface (USBB) Rev: 3.2.0.18 27.1 Features • • • • • • • • 27.2 Compatible with the USB 2.0 specification Supports High (480Mbit/s), Full (12Mbit/s) and Low (1.
AT32UC3A3 Table 27-2. 27.3 Example of Configuration of Pipes/Endpoints Using the Whole DPRAM Pipe/Endpoint Mnemonic Size Nb. Banks 1 PEP1 512 bytes 2 2 PEP2 512 bytes 2 3 PEP3 256 bytes 1 Block Diagram The USBB provides a hardware device to interface a USB link to a data flow stored in a dual-port RAM (DPRAM). The UTMI transceiver requires an external 12MHz clock as a reference to its internal 480MHz PLL.
AT32UC3A3 27.4 Application Block Diagram Depending on the USB operating mode (device-only, reduced-host modes) and the power source (bus-powered or self-powered), there are different typical hardware implementations. 27.4.1 27.4.1.1 Device Mode Bus-Powered device Figure 27-2. Bus-Powered Device Application Block Diagram VDD 3.3 V Regulator USB I/O Controller 2.
AT32UC3A3 27.4.1.2 Self-Powered device Figure 27-3. Self-powered Device Application Block Diagram USB I/O Controller 2.0 Core USB_VBUS USB Connector USB_ID VBus USB_VBOF ID DMFS 39 ohms DPFS 39 ohms UTMI D+ DMHS GND DPHS 27.4.2 D- Host Mode Figure 27-4. Host Application Block Diagram VDD 5V DC/DC Generator USB I/O Controller 2.
AT32UC3A3 27.5 I/O Lines Description Table 27-3.
AT32UC3A3 27.6 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 27.6.1 I/O Lines The USB_VBOF and USB_ID pins are multiplexed with I/O Controller lines and may also be multiplexed with lines of other peripherals. In order to use them with the USB, the user must first configure the I/O Controller to assign them to their USB peripheral functions.
AT32UC3A3 27.7 Functional Description 27.7.1 USB General Operation 27.7.1.1 Introduction After a hardware reset, the USBB is disabled. When enabled, the USBB runs either in device mode or in host mode according to the ID detection. If the USB_ID pin is not connected to ground, the USB_ID Pin State bit in the General Status register (USBSTA.ID) is set (the internal pull-up resistor of the USB_ID pin must be enabled by the I/O Controller) and device mode is engaged. The USBSTA.
AT32UC3A3 After writing a one to USBCON.USBE, the USBB enters the Device or the Host mode (according to the ID detection) in idle state. The USBB can be disabled at any time by writing a zero to USBCON.USBE. In fact, writing a zero to USBCON.USBE acts as a hardware reset, except that the OTGPADE, VBUSPO, FRZCLK, UIDE, UIMOD and, LS bits are not reset. 27.7.1.3 Interrupts One interrupt vector is assigned to the USB interface. Figure 27-6 on page 632 shows the structure of the USB interrupt system.
AT32UC3A3 Figure 27-6. Interrupt System USBSTA.IDTI USBCON.IDTE USBSTA.VBUSTI USBCON.VBUSTE USBSTA.SRPI UESTAX.TXINI USBCON.SRPE UECONX.TXINE USBSTA.VBERRI UECONX.RXOUTE USBSTA.BCERRI UECONX.RXSTPE USBSTA.ROLEEXI UECONX.UNDERFE USBSTA.HNPERRI UECONX.NAKOUTE USBSTA.STOI UESTAX.RXOUTI USBCON.VBERRE UESTAX.RXSTPI USB General Interrupt USBCON.BCERRE UESTAX.UNDERFI USBCON.ROLEEXE UESTAX.NAKOUTI USBCON.HNPERRE UESTAX.HBISOINERRI USBCON.STOE UECONX.HBISOINERRE UESTAX.NAKINI UECONX.
AT32UC3A3 The processing general interrupts are: • The ID Transition Interrupt (IDTI) • The VBus Transition Interrupt (VBUSTI) • The Role Exchange Interrupt (ROLEEXI) The exception general interrupts are: • The VBus Error Interrupt (VBERRI) • The B-Connection Error Interrupt (BCERRI) • The Suspend Time-Out Interrupt (STOI) 27.7.1.4 MCU Power modes •Run mode In this mode, all MCU clocks can run, including the USB clock. •Idle mode In this mode, the CPU is halted, i.e. the CPU clock is stopped.
AT32UC3A3 Moreover, when FRZCLK is written to one, only the asynchronous interrupt sources may trigger the USB interrupt: • The ID Transition Interrupt (IDTI) • The VBus Transition Interrupt (VBUSTI) • The Wake-up Interrupt (WAKEUP) • The Host Wake-up Interrupt (HWUPI) •USB Suspend mode In peripheral mode, the Suspend Interrupt bit in the Device Global Interrupt register (UDINT.SUSP)indicates that the USB line is in the suspend mode.
AT32UC3A3 To free its memory, the user shall write a zero to the UECFGn.ALLOC bit. The n+1 pipe/endpoint memory window then slides down and its data is lost. Note that the following pipe/endpoint memory windows (from n+2) does not slide. Figure 27-7 on page 635 illustrates the allocation and reorganization of the DPRAM in a typical example. Figure 27-7.
AT32UC3A3 FIFO size (i.e. the DPRAM size), so the value of CFGOK does not consider memory allocation conflicts. 27.7.1.7 Pad Suspend Figure 27-8 on page 636 shows the pad behavior. Figure 27-8. Pad Behavior USBE = 1 & DETACH = 0 & Suspend Idle USBE = 0 | DETACH = 1 | Suspend Active • In the Idle state, the pad is put in low power consumption mode, i.e., the differential receiver of the USB pad is off, and internal pull-down with strong value(15K) are set in both DP/DM to avoid floating lines.
AT32UC3A3 Moreover, the pad goes to the Idle state if the macro is disabled or if the DETACH bit is written to one. It returns to the Active state when USBE is written to one and DETACH is written to zero. 27.7.1.8 Plug-In detection The USB connection is detected from the USB_VBUS pad. Figure 27-10 on page 637 shows the architecture of the plug-in detector. Figure 27-10.
AT32UC3A3 Figure 27-11. ID Detection Input Block Diagram RPU VDD 1 USB_ID 0 UIMOD ID IDTI USBSTA USBSTA USBCON UIDE USBCON I/O Controller The USB mode (device or host) can be either detected from the USB_ID pin or software selected by writing to the UIMOD bit, according to the UIDE bit. This allows the USB_ID pin to be used as a general purpose I/O pin even when the USB interface is enabled. By default, the USB_ID pin is selected (UIDE is written to one) and the USBB is in device mode (UBSTA.
AT32UC3A3 27.7.2 27.7.2.1 USB Device Operation Introduction In device mode, the USBB supports hi- full- and low-speed data transfers. In addition to the default control endpoint, seven endpoints are provided, which can be configured with the types isochronous, bulk or interrupt, as described in .Table 27-1 on page 624. The device mode starts in the Idle state, so the pad consumption is reduced to the minimum. 27.7.2.2 Power-On and reset Figure 27-12 on page 639 describes the USBB device mode main states.
AT32UC3A3 • The default control endpoint is reset (see Section 27.7.2.4 for more details). • The data toggle sequence of the default control endpoint is cleared. • At the end of the reset process, the End of Reset (EORST) bit in UDINT interrupt is set. • During a reset, the USBB automatically switches to the Hi-Speed mode if the host is HiSpeed capable (the reset is called a Hi-Speed reset). The user should observe the USBSTA.SPEED field to know the speed running at the end of the reset (EORST is one). 27.
AT32UC3A3 Figure 27-13. Endpoint Activation Algorithm Endpoint Activation Enable the endpoint. EPENn = 1 Configure the endpoint: - type - direction - size - number of banks Allocate the configured DPRAM banks. UECFGn EPTYPE EPDIR EPSIZE EPBK ALLOC CFGOK == 1? Yes Test if the endpoint configuration is correct. No Endpoint Activated ERROR As long as the endpoint is not correctly configured (CFGOK is zero), the controller does not acknowledge the packets sent by the host to this endpoint.
AT32UC3A3 27.7.2.7 Suspend and wake-up When an idle USB bus state has been detected for 3 ms, the controller set the Suspend (SUSP) interrupt bit in UDINT. The user may then write a one to the FRZCLK bit to reduce power consumption. The MCU can also enter the Idle or Frozen sleep mode to lower again power consumption. To recover from the Suspend mode, the user shall wait for the Wake-Up (WAKEUP) interrupt bit, which is set when a non-idle event is detected, then write a zero to FRZCLK.
AT32UC3A3 •Special considerations for control endpoints If a SETUP packet is received into a control endpoint for which a STALL is requested, the Received SETUP Interrupt (RXSTPI) bit in UESTAn is set and STALLRQ and STALLEDI are cleared. The SETUP has to be ACKed. This management simplifies the enumeration process management. If a command is not supported or contains an error, the user requests a STALL and can return to the main task, waiting for the next SETUP request.
AT32UC3A3 Figure 27-14. Control Write SETUP USB Bus DATA SETUP OUT STATUS OUT IN IN NAK RXSTPI HW SW RXOUTI HW SW HW SW TXINI SW •Control read Figure 27-15 on page 644 shows a control read transaction. The USBB has to manage the simultaneous write requests from the CPU and the USB host. Figure 27-15.
AT32UC3A3 27.7.2.12 Management of IN endpoints •Overview IN packets are sent by the USB device controller upon IN requests from the host. All the data can be written which acknowledges or not the bank when it is full. The endpoint must be configured first. The TXINI bit is set at the same time as FIFOCON when the current bank is free. This triggers an EPnINT interrupt if the Transmitted IN Data Interrupt Enable (TXINE) bit in UECONn is one.
AT32UC3A3 Figure 27-17. Example of an IN Endpoint with 2 Data Banks DATA (bank 0) IN ACK IN DATA (bank 1) ACK HW TXINI FIFOCON SW write data to CPU BANK 0 SW SW write data to CPU BANK 1 SW SW write data to CPU BANK0 •Detailed description The data is written, following the next flow: • When the bank is empty, TXINI and FIFOCON are set, what triggers an EPnINT interrupt if TXINE is one. • The user acknowledges the interrupt by clearing TXINI.
AT32UC3A3 Figure 27-18. Abort Algorithm Endpoint Abort Disable the TXINI interrupt. TXINEC = 1 NBUSYBK == 0? Yes Abort is based on the fact that no bank is busy, i.e., that nothing has to be sent No EPRSTn = 1 KILLBKS = 1 Yes KILLBK == 1? Kill the last written bank. Wait for the end of the procedure No Abort Done 27.7.2.13 Management of OUT endpoints •Overview OUT packets are sent by the host. All the data can be read which acknowledges or not the bank when it is empty.
AT32UC3A3 Figure 27-19. Example of an OUT Endpoint with one Data Bank DATA (bank 0) OUT NAK ACK OUT DATA (bank 0) ACK HW RXOUTI HW SW SW read data from CPU BANK 0 FIFOCON read data from CPU BANK 0 SW Figure 27-20.
AT32UC3A3 responds to the OUT/DATA transaction with an ACK handshake when the endpoint accepted the data successfully and has room for another data payload (the second bank is free). 27.7.2.14 Underflow This error exists only for isochronous IN/OUT endpoints. It set the Underflow Interrupt (UNDERFI) bit in UESTAn, what triggers an EPnINT interrupt if the Underflow Interrupt Enable (UNDERFE) bit is one. An underflow can occur during IN stage if the host attempts to read from an empty bank.
AT32UC3A3 For instance, if NBTRANS is three (three transactions per micro-frame), if only the first IN token (among 3) is well received by the USBB, then the two last banks will be discarded. 27.7.2.18 CRC error This error exists only for isochronous OUT endpoints. It set the CRC Error Interrupt (CRCERRI) bit in UESTAn, what triggers an EPnINT interrupt if the CRC Error Interrupt Enable (CRCERRE) bit is one. A CRC error can occur during OUT stage if the USBB detects a corrupted received packet.
AT32UC3A3 • The NAKed OUT Interrupt (NAKOUTI) • The High-bandwidth isochronous IN error Interrupt (HBISOINERRI) if the high-bandwidth isochronous feature is supported by the device (see the UFEATURES register for this) • The NAKed IN Interrupt (NAKINI) • The High-bandwidth isochronous IN Flush error Interrupt (HBISOFLUSHI) if the highbandwidth isochronous feature is supported by the device (see the UFEATURES register for this) • The Overflow Interrupt (OVERFI) • The STALLed Interrupt (STALLEDI) • The CRC Er
AT32UC3A3 27.7.3 27.7.3.1 USB Host Operation Description of pipes For the USBB in host mode, the term “pipe” is used instead of “endpoint” (used in device mode). A host pipe corresponds to a device endpoint, as described by the Figure 27-21 on page 652 from the USB specification. Figure 27-21. USB Communication Flow In host mode, the USBB associates a pipe to a device endpoint, considering the device configuration descriptors. 27.7.3.
AT32UC3A3 sumption. The USB pad should be in the Idle state. Once a device is connected, the macro enters the Ready state, what does not require the USB clock to be activated. The controller enters the Suspend state when the USB bus is in a “Suspend” state, i.e., when the host mode does not generate the “Start of Frame (SOF)”. In this state, the USB consumption is minimal. The host mode exits the Suspend state when starting to generate the SOF over the USB line. 27.7.3.
AT32UC3A3 27.7.3.6 Pipe activation The pipe is maintained inactive and reset (see Section 27.7.3.5 for more details) as long as it is disabled (PENn is zero). The Data Toggle Sequence field (DTSEQ) is also reset. The algorithm represented on Figure 27-23 on page 654 must be followed in order to activate a pipe. Figure 27-23. Pipe Activation Algorithm Pipe Activation PENn = 1 Enable the pipe.
AT32UC3A3 When the host controller sends an USB reset, the UHADDRPn field is reset by hardware and the following host requests will be performed using the default device address 0. 27.7.3.8 Remote wake-up The controller host mode enters the Suspend state when the UHCON.SOFE bit is written to zero. No more “Start of Frame” is sent on the USB bus and the USB device enters the Suspend state 3ms later. The device awakes the host by sending an Upstream Resume (Remote Wake-Up feature).
AT32UC3A3 RXINI shall be cleared by software (by writing a one to the Received IN Data Interrupt Clear bit in the Pipe n Control Clear register(UPCONnCLR.RXINIC)) to acknowledge the interrupt, what has no effect on the pipe FIFO. The user then reads from the FIFO (see ”USB Pipe/Endpoint n FIFO Data Register (USBFIFOnDATA)” on page 747) and clears the FIFOCON bit (by writing a one to the FIFO Control Clear (FIFOCONC) bit in UPCONnCLR) to free the bank.
AT32UC3A3 The Transmitted OUT Data Interrupt (TXOUTI) bit in UPSTAn is set at the same time as FIFOCON when the current bank is free. This triggers a PnINT interrupt if the Transmitted OUT Data Interrupt Enable (TXOUTE) bit in UPCONn is one. TXOUTI shall be cleared by software (by writing a one to the Transmitted OUT Data Interrupt Clear (TXOUTIC) bit in UPCONnCLR) to acknowledge the interrupt, what has no effect on the pipe FIFO.
AT32UC3A3 Figure 27-27. Example of an OUT Pipe with two Data Banks and no Bank Switching Delay OUT DATA (bank 0) ACK OUT DATA (bank 1) ACK HW SW TXOUTI SW write data to CPU SW BANK 0 FIFOCON SW write data to CPU BANK 1 write data to CPU BANK0 SW Figure 27-28. Example of an OUT Pipe with two Data Banks and a Bank Switching Delay OUT DATA (bank 0) ACK OUT DATA (bank 1) ACK HW TXOUTI SW FIFOCON 27.7.3.
AT32UC3A3 • The USB Reset Sent Interrupt (RSTI) • The Downstream Resume Sent Interrupt (RSMEDI) • The Upstream Resume Received Interrupt (RXRSMI) • The Host Start of Frame Interrupt (HSOFI) • The Host Wake-Up Interrupt (HWUPI) • The Pipe n Interrupt (PnINT) • The DMA Channel n Interrupt (DMAnINT) There is no exception host global interrupt.
AT32UC3A3 27.7.4 27.7.4.1 USB DMA Operation Introduction USB packets of any length may be transferred when required by the USBB. These transfers always feature sequential addressing. These two characteristics mean that in case of high USBB throughput, both HSB ports will benefit from “incrementing burst of unspecified length” since the average access latency of HSB slaves can then be reduced.
AT32UC3A3 Figure 27-29. Example of DMA Chained List Transfer Descriptor USB DMA Channel X Registers (Current Transfer Descriptor) Next Descriptor Address Next Descriptor Address HSB Address Transfer Descriptor Control Next Descriptor Address HSB Address HSB Address Transfer Descriptor Control Next Descriptor Address Control HSB Address Status Control NULL Memory Area Data Buffer 1 Data Buffer 2 Data Buffer 3 27.7.4.
AT32UC3A3 •Single-block transfer programming example for OUT transfer : The following sequence may be used: • Configure the targerted endpoint (source) as OUT type, and set the automatic bank switching for this endpoint in the UECFGn register to handle multiple OUT packet. • Write the starting destination address in the UDDMAnADDR register. • There is no need to program the UDDMAnNEXTDESC register. • Program the channel byte length in the UDDMAnCONTROL register.
AT32UC3A3 •Programming example for multi-block dma transfer : run and link at end of buffer The idea is to run first a single block transfer followed automatically by a linked list of DMA. The following sequence may be used: • Configure the targerted endpoint (source) as OUT type, and set the automatic bank switching for this endpoint in the UECFGn register to handle multiple OUT packet. • Set up the chain of linked list of descripor in memory.
AT32UC3A3 • Set up the chain of linked list of descripor in memory. Each descriptor is composed of 3 items : channel next descriptor address, channel destination address and channel control. The last descriptor should be programmed according to row 2 as shown in Figure 27-6 on page 714. • Program the UDDMAnNEXTDESC register. • Program the UDDMAnCONTROL according to Row 3 as shown in Figure 27-6 on page 714. The UDDMAnSTATUS.CHEN bit is 0 and the UDDMAnSTATUS.
AT32UC3A3 27.8 User Interface Table 27-4.
AT32UC3A3 Table 27-4.
AT32UC3A3 Table 27-4.
AT32UC3A3 Table 27-4.
AT32UC3A3 Table 27-4.
AT32UC3A3 Table 27-4.
AT32UC3A3 Table 27-4.
AT32UC3A3 Table 27-5.
AT32UC3A3 27.8.1 USB General Registers 27.8.1.
AT32UC3A3 This bit can be written even if FRZCLK is one. • FRZCLK: Freeze USB Clock 1: The clock input are disabled (the resume detection is still active).This reduces power consumption. Unless explicitly stated, all registers then become read-only. 0: The clock inputs are enabled. This bit can be written even if USBE is zero. Disabling the USBB (by writing a zero to the USBE bit) does not reset this bit, but this freezes the clock inputs whatever its value.
AT32UC3A3 27.8.1.2 General Status Register Register Name: USBSTA Access Type: Read-Only Offset: 0x0804 Reset Value: 0x00000400 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - CLKUSABLE VBUS ID VBUSRQ - 7 6 2 1 0 VBUSTI IDTI STOI SPEED 5 4 3 ROLEEXI BCERRI VBERRI • CLKUSABLE: UTMI Clock Usable This bit is set when the UTMI 30MHz is usable.
AT32UC3A3 • STOI: Suspend Time-Out Interrupt This bit is set when a time-out error (more than 200ms) has been detected after a suspend. This triggers a USB interrupt if STOE is one. This bit is cleared when the UBSTACLR.STOIC bit is written to one. This bit shall only be used in host mode. • ROLEEXI: Role Exchange Interrupt This bit is set when the USBB has successfully switched its mode because of an negotiation (host to device or device to host). This triggers a USB interrupt if ROLEEXE is one.
AT32UC3A3 27.8.1.3 General Status Clear Register Register Name: USBSTACLR Access Type: Write-Only Offset: 0x0808 Read Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - VBUSRQC - 7 6 5 4 3 2 1 0 ROLEEXIC BCERRIC VBERRIC VBUSTIC IDTIC STOIC Writing a one to a bit in this register will clear the corresponding bit in UBSTA.
AT32UC3A3 27.8.1.
AT32UC3A3 27.8.1.5 Version Register Register Name: UVERS Access Type: Read-Only Offset: 0x0818 Read Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated.
AT32UC3A3 27.8.1.
AT32UC3A3 • DMAFIFOWORDDEPTH: DMA FIFO Depth in Words This field indicates the DMA FIFO depth controller in words: DMAFIFOWORDDEPTH DMA FIFO Depth in Words 0 0 0 0 16 0 0 0 1 1 0 0 1 0 2 ... 1 1 1 1 15 • DMABUFFERSIZE: DMA Buffer Size 1: The DMA buffer size is 24bits. 0: The DMA buffer size is 16bits.
AT32UC3A3 27.8.1.7 Address Size Register Register Name: UADDRSIZE Access Type: Read-Only Offset: 0x0820 Read Value: - 31 30 29 28 27 26 25 24 18 17 16 10 9 8 2 1 0 UADDRSIZE[31:24] 23 22 21 20 19 UADDRSIZE[23:16] 15 14 13 12 11 UADDRSIZE[15:8] 7 6 5 4 3 UADDRSIZE[7:0] • UADDRSIZE: IP PB Address Size This field indicates the size of the PB address space reserved for the USBB IP interface.
AT32UC3A3 27.8.1.8 Name Register 1 Register Name: UNAME1 Access Type: Read-Only Offset: 0x0824 Read Value: - 31 30 29 28 27 26 25 24 18 17 16 10 9 8 2 1 0 UNAME1[31:24] 23 22 21 20 19 UNAME1[23:16] 15 14 13 12 11 UNAME1[15:8] 7 6 5 4 3 UNAME1[7:0] • UNAME1: IP Name Part One This field indicates the first part of the ASCII-encoded name of the USBB IP.
AT32UC3A3 27.8.1.9 Name Register 2 Register Name: UNAME2 Access Type: Read-Only Offset: 0x0828 Read Value: 31 30 29 28 27 26 25 24 18 17 16 10 9 8 2 1 0 UNAME2[31:24] 23 22 21 20 19 UNAME2[23:16] 15 14 13 12 11 UNAME2[15:8] 7 6 5 4 3 UNAME2[7:0] • UNAME2: IP Name Part Two This field indicates the second part of the ASCII-encoded name of the USBB IP.
AT32UC3A3 27.8.1.10 Finite State Machine Status Register Register Name: USBFSM Access Type: Read-Only Offset: 0x082C Read Value: 0x00000009 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - DRDSTATE • DRDSTATE This field indicates the state of the USBB.
AT32UC3A3 DRDSTATE Description 13 b_wait_acon: In this state, the B-device waits for the A-device to signal a connect before becoming B-Host. 14 b_host: In this state, the B-device acts as the Host. 15 b_srp_init: In this state, the B-device attempts to start a session using the SRP protocol.
AT32UC3A3 27.8.2 USB Device Registers 27.8.2.
AT32UC3A3 • SPDCONF: Speed Configuration This field contains the peripheral speed. SPDCONF Speed 0 0 Normal mode: the peripheral starts in full-speed mode and performs a high-speed reset to switch to the high-speed mode if the host is high-speed capable. 0 1 reserved, do not use this configuration 1 0 reserved, do not use this configuration 1 1 Full-speed: the peripheral remains in full-speed mode whatever is the host speed capability.
AT32UC3A3 27.8.2.
AT32UC3A3 • SOF: Start of Frame Interrupt This bit is set when a USB “Start of Frame” PID (SOF) has been detected (every 1 ms). This triggers a USB interrupt if SOFE is one. The FNUM field is updated. In High-speed mode, the MFNUM field is cleared. This bit is cleared when the UDINTCLR.SOFC bit is written to one to acknowledge the interrupt. • MSOF: Micro Start of Frame Interrupt This bit is set in High-speed mode when a USB “Micro Start of Frame” PID (SOF) has been detected (every 125 us).
AT32UC3A3 27.8.2.3 Device Global Interrupt Clear Register Register Name: UDINTCLR Access Type: Write-Only Offset: 0x0008 Read Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - UPRSMC EORSMC WAKEUPC EORSTC SOFC MSOFC SUSPC Writing a one to a bit in this register will clear the corresponding bit in UDINT.
AT32UC3A3 27.8.2.
AT32UC3A3 27.8.2.
AT32UC3A3 27.8.2.
AT32UC3A3 27.8.2.
AT32UC3A3 27.8.2.
AT32UC3A3 27.8.2.9 Device Frame Number Register Register Name: UDFNUM Access Type: Read-Only Offset: 0x0020 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 FNCERR - 7 6 2 1 0 FNUM[10:5] 5 FNUM[4:0] 4 3 MFNUM • FNCERR: Frame Number CRC Error This bit is set when a corrupted frame number (or micro-frame number) is received.
AT32UC3A3 27.8.2.10 Endpoint n Configuration Register Register Name: UECFGn, n in [0..
AT32UC3A3 • AUTOSW: Automatic Switch This bit is cleared upon receiving a USB reset. 1: The automatic bank switching is enabled. 0: The automatic bank switching is disabled. • EPDIR: Endpoint Direction This bit is cleared upon receiving a USB reset. 1: The endpoint direction is IN (nor for control endpoints). 0: The endpoint direction is OUT. • EPSIZE: Endpoint Size This field shall be written to select the size of each endpoint bank. The maximum size of each endpoint is specified in Table 271 on page 624.
AT32UC3A3 27.8.2.11 Endpoint n Status Register Register Name: UESTAn, n in [0..
AT32UC3A3 • CURRBK: Current Bank This bit is set for non-control endpoints, to indicate the current bank: CURRBK Current Bank 0 0 Bank0 0 1 Bank1 1 0 Bank2 if supported (see Table 27-1 on page 624). 1 1 Reserved This field may be updated one clock cycle after the RWALL bit changes, so the user should not poll this field as an interrupt bit.
AT32UC3A3 For OUT transfers, this value indicates the last data toggle sequence received on the current bank. By default DTSEQ is 0b01, as if the last data toggle sequence was Data1, so the next sent or expected data toggle sequence should be Data0. For High-bandwidth isochronous endpoint, an EPnINT interrupt is triggered if: - MDATAE is one and a MData packet has been received (DTSEQ=MData and RXOUTI is one).
AT32UC3A3 An underflow can occur during IN stage if the host attempts to read from an empty bank. A zero-length packet is then automatically sent by the USBB. An underflow can also occur during OUT stage if the host sends a packet while the bank is already full. Typically, the CPU is not fast enough. The packet is lost. Shall be cleared by writing a one to the UNDERFIC bit. This will acknowledge the interrupt.
AT32UC3A3 27.8.2.12 Endpoint n Status Clear Register Register Name: UESTAnCLR, n in [0..
AT32UC3A3 27.8.2.13 Endpoint n Status Set Register Register Name: UESTAnSET, n in [0..
AT32UC3A3 27.8.2.14 Endpoint n Control Register Register Name: UECONn, n in [0..
AT32UC3A3 • FIFOCON: FIFO Control For control endpoints: The FIFOCON and RWALL bits are irrelevant. The software shall therefore never use them on these endpoints. When read, their value is always 0. For IN endpoints: This bit is set when the current bank is free, at the same time as TXINI. This bit is cleared (by writing a one to the FIFOCONC bit) to send the FIFO data and to switch to the next bank. For OUT endpoints: This bit is set when the current bank is full, at the same time as RXOUTI.
AT32UC3A3 This bit is cleared when the HBISOFLUSHEC bit disable the HBISOFLUSHI interrupt. Look at the UFEATURES register to know if the high-bandwidth isochronous feature is supported by the device. • NAKOUTE: NAKed OUT Interrupt Enable This bit is set when the NAKOUTES bit is written to one. This will enable the NAKed OUT interrupt (NAKOUTI). This bit is cleared when the NAKOUTEC bit is written to one. This will disable the NAKed OUT interrupt (NAKOUTI).
AT32UC3A3 27.8.2.15 Endpoint n Control Clear Register Register Name: UECONnCLR, n in [0..
AT32UC3A3 27.8.2.16 Endpoint n Control Set Register Register Name: UECONnSET, n in [0..
AT32UC3A3 27.8.2.17 Device DMA Channel n Next Descriptor Address Register Register Name: UDDMAnNEXTDESC, n in [1..
AT32UC3A3 27.8.2.18 Device DMA Channel n HSB Address Register Register Name: UDDMAnADDR, n in [1..7] Access Type: Read/Write Offset: 0x0314 + (n - 1) * 0x10 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 18 17 16 10 9 8 2 1 0 HSBADDR[31:24] 23 22 21 20 19 HSBADDR[23:16] 15 14 13 12 11 HSBADDR[15:8] 7 6 5 4 3 HSBADDR[7:0] • HSBADDR: HSB Address This field determines the HSB bus current address of a channel transfer.
AT32UC3A3 27.8.2.19 Device DMA Channel n Control Register Register Name: UDDMAnCONTROL, n in [1..
AT32UC3A3 • BUFFCLOSEINEN: Buffer Close Input Enable For Bulk and Interrupt endpoint, writing a one to this bit will automatically close the current DMA transfer at the end of the USB OUT data transfer (received short packet). For Full-speed Isochronous, it does not make sense, so BUFFCLOSEINEN should be left to zero. For high-speed OUT isochronous, it may make sense. In that case, if BUFFCLOSEINEN is written to one, the current DMA transfer is closed when the received PID packet is not MDATA.
AT32UC3A3 27.8.2.20 Device DMA Channel n Status Register Register Name: UDDMAnSTATUS, n in [1..
AT32UC3A3 0: the DMA channel no longer transfers data, and may load the next descriptor if the UDDMAnCONTROL.LDNXTCHDESCEN bit is zero. 1: the DMA channel is currently enabled and transfers data upon request. If a channel request is currently serviced when the UDDMAnCONTROL.CHEN bit is written to zero, the DMA FIFO buffer is drained until it is empty, then this status bit is cleared.
AT32UC3A3 27.8.3 USB Host Registers 27.8.3.1 Host General Control Register Register Name: UHCON Access Type: Read/Write Offset: 0x0400 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - RESUME RESET SOFE 7 6 5 4 3 2 1 0 - - - - - - - - SPDCONF • SPDCONF: Speed Configuration This field contains the host speed capability.
AT32UC3A3 27.8.3.
AT32UC3A3 • DDISCI: Device Disconnection Interrupt This bit is set when the device has been removed from the USB bus. This bit is cleared when the DDISCIC bit is written to one. • DCONNI: Device Connection Interrupt This bit is set when a new device has been connected to the USB bus. This bit is cleared when the DCONNIC bit is written to one.
AT32UC3A3 27.8.3.3 Host Global Interrupt Clear Register Register Name: UHINTCLR Access Type: Write-Only Offset: 0x0408 Read Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - HWUPIC HSOFIC RXRSMIC RSMEDIC RSTIC DDISCIC DCONNIC Writing a one to a bit in this register will clear the corresponding bit in UHINT.
AT32UC3A3 27.8.3.
AT32UC3A3 27.8.3.
AT32UC3A3 27.8.3.
AT32UC3A3 27.8.3.
AT32UC3A3 27.8.3.
AT32UC3A3 27.8.3.9 Host Address 1 Register Register Name: UHADDR1 Access Type: Read/Write Offset: 0x0424 Reset Value: 0x00000000 31 30 29 28 - 23 22 21 20 - 25 24 19 18 17 16 10 9 8 2 1 0 UHADDRP2 14 13 12 - 7 26 UHADDRP3 - 15 27 11 UHADDRP1 6 5 4 3 UHADDRP0 • UHADDRP3: USB Host Address This field contains the address of the Pipe3 of the USB Device. This field is cleared when a USB reset is requested.
AT32UC3A3 27.8.3.10 Host Address 2 Register Register Name: UHADDR2 Access Type: Read/Write Offset: 0x0428 Reset Value: 0x00000000 31 30 29 28 - 23 22 21 20 - 25 24 19 18 17 16 10 9 8 2 1 0 UHADDRP6 14 13 12 - 7 26 UHADDRP7 - 15 27 11 UHADDRP5 6 5 4 3 UHADDRP4 • UHADDRP7: USB Host Address This field contains the address of the Pipe7 of the USB Device. This field is cleared when a USB reset is requested.
AT32UC3A3 27.8.3.11 Pipe Enable/Reset Register Register Name: UPRST Access Type: Read/Write Offset: 0x0041C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 PRST7 PRST6 PRST5 PRST4 PRST3 PRST2 PRST1 PRST0 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 PEN7 PEN6 PEN5 PEN4 PEN3 PEN2 PEN1 PEN0 • PRSTn: Pipe n Reset Writing a one to this bit will reset the Pipe n FIFO.
AT32UC3A3 27.8.3.12 Pipe n Configuration Register Register Name: UPCFGn, n in [0..
AT32UC3A3 PTYPE Pipe Type 0 1 Isochronous 1 0 Bulk 1 1 Interrupt This field is cleared upon sending a USB reset. • AUTOSW: Automatic Switch This bit is cleared upon sending a USB reset. 1: The automatic bank switching is enabled. 0: The automatic bank switching is disabled. • PTOKEN: Pipe Token This field contains the endpoint token. PTOKEN Endpoint Direction 00 SETUP 01 IN 10 OUT 11 reserved • PSIZE: Pipe Size This field contains the size of each pipe bank.
AT32UC3A3 • ALLOC: Pipe Memory Allocate Writing a one to this bit will allocate the pipe memory. Writing a zero to this bit will free the pipe memory. This bit is cleared when a USB Reset is requested. Refer to the DPRAM Management chapter for more details.
AT32UC3A3 27.8.3.13 Pipe n Status Register Register Name: UPSTAn, n in [0..
AT32UC3A3 CURRBK Current Bank 0 1 Bank1 1 0 Bank2 if supported (see Table 27-1 on page 624). 1 1 Reserved This field may be updated 1 clock cycle after the RWALL bit changes, so the user shall not poll this field as an interrupt bit. • NBUSYBK: Number of Busy Banks This field indicates the number of busy bank. For OUT pipe, this field indicates the number of busy bank(s), filled by the user, ready for OUT transfer. When all banks are busy, this triggers an PnINT interrupt if UPCONn.
AT32UC3A3 This bit is cleared when the NAKEDIC bit written to one. • PERRI: Pipe Error Interrupt This bit is set when an error occurs on the current bank of the pipe. This triggers an interrupt if the PERRE bit is set. Refers to the UPERRn register to determine the source of the error. This bit is cleared when the error source bit is cleared. • TXSTPI: Transmitted SETUP Interrupt This bit is set, for Control endpoints, when the current SETUP bank is free and can be filled.
AT32UC3A3 27.8.3.14 Pipe n Status Clear Register Register Name: UPSTAnCLR, n in [0..
AT32UC3A3 27.8.3.15 Pipe n Status Set Register Register Name: UPSTAnSET, n in [0..
AT32UC3A3 27.8.3.16 Pipe n Control Register Register Name: UPCONn, n in [0..
AT32UC3A3 • RXSTALLDE: Received STALLed Interrupt Enable This bit is set when the RXSTALLDES bit is written to one. This will enable the Transmitted IN Data interrupt (RXSTALLDE). This bit is cleared when the RXSTALLDEC bit is written to one. This will disable the Transmitted IN Data interrupt (RXSTALLDE). • CRCERRE: CRC Error Interrupt Enable This bit is set when the CRCERRES bit is written to one. This will enable the Transmitted IN Data interrupt (CRCERRE).
AT32UC3A3 27.8.3.17 Pipe n Control Clear Register Register Name: UPCONnCLR, n in [0..
AT32UC3A3 27.8.3.18 Pipe n Control Set Register Register Name: UPCONnSET, n in [0..
AT32UC3A3 27.8.3.19 Pipe n IN Request Register Register Name: UPINRQn, n in [0..7] Access Type: Read/Write Offset: 0x0650 + (n * 0x04) Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - INMODE 7 6 5 4 3 2 1 0 INRQ • INMODE: IN Request Mode Writing a one to this bit will allow the USBB to perform infinite IN requests when the Pipe is not frozen.
AT32UC3A3 27.8.3.20 Pipe n Error Register Register Name: UPERRn, n in [0..
AT32UC3A3 27.8.3.21 Host DMA Channel n Next Descriptor Address Register Register Name: UHDMAnNEXTDESC, n in [1..7] Access Type: Read/Write Offset: 0x0710 + (n - 1) * 0x10 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 18 17 16 10 9 8 3 2 1 0 - - - - NXTDESCADDR[31:24] 23 22 21 20 19 NXTDESCADDR[23:16] 15 14 13 12 11 NXTDESCADDR[15:8] 7 6 5 NXTDESCADDR[7:4] 4 Same as Section 27.8.2.17.
AT32UC3A3 27.8.3.22 Host DMA Channel n HSB Address Register Register Name: UHDMAnADDR, n in [1..7] Access Type: Read/Write Offset: 0x0714 + (n - 1) * 0x10 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 18 17 16 10 9 8 2 1 0 HSBADDR[31:24] 23 22 21 20 19 HSBADDR[23:16] 15 14 13 12 11 HSBADDR[15:8] 7 6 5 4 3 HSBADDR[7:0] Same as Section 27.8.2.18.
AT32UC3A3 27.8.3.23 USB Host DMA Channel n Control Register Register Name: UHDMAnCONTROL, n in [1..7] Access Type: Read/Write Offset: 0x0718 + (n - 1) * 0x10 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 18 17 16 CHBYTELENGTH[15:8] 23 22 21 20 19 CHBYTELENGTH[7:0] 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 BURSTLOC KEN DESCLD IRQEN EOBUFF IRQEN EOTIRQEN DMAENDEN BUFFCLOSE INEN LDNXTCHD ESCEN CHEN Same as Section 27.8.2.19.
AT32UC3A3 27.8.3.24 USB Host DMA Channel n Status Register Register Name: UHDMAnSTATUS, n in [1..7] Access Type: Read/Write Offset: 0x071C + (n - 1) * 0x10 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 18 17 16 CHBYTECNT[15:8] 23 22 21 20 19 CHBYTECNT[7:0] 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - DESCLD STA EOCHBUFFS TA EOTSTA - - CHACTIVE CHEN Same as Section 27.8.2.20.
AT32UC3A3 27.8.4 USB Pipe/Endpoint n FIFO Data Register (USBFIFOnDATA) The application has access to the physical DPRAM reserved for the Endpoint/Pipe through a 64KB virtual address space. The application can access anywhere in the virtual 64KB segment (linearly or fixedly) as the DPRAM Fifo address increment is fully handled by hardware. Byte, half-word and word access are supported. Data should be access in a big-endian way.
AT32UC3A3 27.9 Module Configuration The specific configuration for the USBB instance is listed in the following tables. The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. Table 27-7. Module Clock Name Module name Clock name Clock name USBB CLK_USBB_HSB CLK_USBB_PB Table 27-8.
AT32UC3A3 28. Timer/Counter (TC) Rev: 2.2.3.3 28.
AT32UC3A3 28.3 Block Diagram Figure 28-1.
AT32UC3A3 28.5.2 Power Management If the CPU enters a sleep mode that disables clocks used by the TC, the TC will stop functioning and resume operation after the system wakes up from sleep mode. 28.5.3 Clocks The clock for the TC bus interface (CLK_TC) is generated by the Power Manager. This clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the TC before disabling the clock, to avoid freezing the TC in an undefined state. 28.5.
AT32UC3A3 28.6.1.3 Clock selection At block level, input clock signals of each channel can either be connected to the external inputs TCLK0, TCLK1 or TCLK2, or be connected to the configurable I/O signals A0, A1 or A2 for chaining by writing to the BMR register. See Figure 28-2 on page 752. Each channel can independently select an internal or external clock source for its counter: • Internal clock signals: TIMER_CLOCK1, TIMER_CLOCK2, TIMER_CLOCK3, TIMER_CLOCK4, TIMER_CLOCK5.
AT32UC3A3 • The clock can be enabled or disabled by the user by writing to the Counter Clock Enable/Disable Command bits in the Channel n Clock Control Register (CCRn.CLKEN and CCRn.CLKDIS). In Capture mode it can be disabled by an RB load event if the Counter Clock Disable with RB Loading bit in CMRn is written to one (CMRn.LDBDIS). In Waveform mode, it can be disabled by an RC Compare event if the Counter Clock Disable with RC Compare bit in CMRn is written to one (CMRn.CPCDIS).
AT32UC3A3 28.6.1.6 Trigger A trigger resets the counter and starts the counter clock. Three types of triggers are common to both modes, and a fourth external trigger is available to each mode. The following triggers are common to both modes: • Software Trigger: each channel has a software trigger, available by writing a one to the Software Trigger Command bit in CCRn (CCRn.SWTRG). • SYNC: each channel has a synchronization signal SYNC. When asserted, this signal has the same effect as a software trigger.
AT32UC3A3 28.6.2.2 Trigger conditions In addition to the SYNC signal, the software trigger and the RC compare trigger, an external trigger can be defined. The TIOA or TIOB External Trigger Selection bit in CMRn (CMRn.ABETRG) selects TIOA or TIOB input signal as an external trigger. The External Trigger Edge Selection bit in CMRn (CMRn.ETREDG) defines the edge (rising, falling or both) detected to generate an external trigger. If CMRn.ETRGEDG is zero (none), the external trigger is disabled.
32072H–AVR32–10/2012 TIOA TIOB SYNC MTIOA MTIOB TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 XC0 XC1 XC2 1 Edge Detector ETRGEDG SWTRG CLKI S R OVF LDRB Edge Detector Edge Detector Capture Register A LDBSTOP S R CLKEN LDRA If RA is Loaded CPCTRG 16-bit Counter RESET Trig CLK Q Q CLKSTA LDBDIS Capture Register B CLKDIS SR Timer/Counter Channel If RA is not Loaded or RB is Loaded ABETRG BURST TCCLKS Compare RC = Register C COVFS LDRBS INT AT32UC3A3
AT32UC3A3 28.6.3 Waveform Operating Mode Waveform operating mode is entered by writing a one to the CMRn.WAVE bit. In Waveform operating mode the TC channel generates one or two PWM signals with the same frequency and independently programmable duty cycles, or generates different types of oneshot or repetitive pulses. In this mode, TIOA is configured as an output and TIOB is defined as an output if it is not used as an external event.
32072H–AVR32–10/2012 TIOB SYNC TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 XC0 XC1 XC2 EEVT Edge Detector EEVTEDG SWTRG ENETRG Trig CLK S R Register A Q CLKSTA Compare RA = OVF WAVSEL RESET 16-bit Counter WAVSEL Q SR Timer/Counter Channel 1 BURST CLKI Compare RC = Compare RB = CPCSTOP CPCDIS Register C CLKDIS Register B R S CLKEN CPAS INT BSWTRG BEEVT BCPB BCPC ASWTRG AEEVT ACPA ACPC O utput Contr oller O utput Cont r oller TCCLKS TIOB M
AT32UC3A3 28.6.3.2 WAVSEL = 0 When CMRn.WAVSEL is zero, the value of CVn is incremented from 0 to 0xFFFF. Once 0xFFFF has been reached, the value of CVn is reset. Incrementation of CVn starts again and the cycle continues. See Figure 28-6 on page 759. An external event trigger or a software trigger can reset the value of CVn. It is important to note that the trigger may occur at any time. See Figure 28-7 on page 760. RC Compare cannot be programmed to generate a trigger in this configuration.
AT32UC3A3 Figure 28-7. WAVSEL= 0 With Trigger Counter Value Counter cleared by compare match with 0xFFFF 0xFFFF RC Counter cleared by trigger RB RA Waveform Examples Time TIOB TIOA 28.6.3.3 WAVSEL = 2 When CMRn.WAVSEL is two, the value of CVn is incremented from zero to the value of RC, then automatically reset on a RC Compare. Once the value of CVn has been reset, it is then incremented and so on. See Figure 28-8 on page 761.
AT32UC3A3 Figure 28-8. WAVSEL = 2 Without Trigger Counter Value 0xFFFF Counter cleared by compare match with RC RC RB RA Waveform Examples Time TIOB TIOA Figure 28-9. WAVSEL = 2 With Trigger Counter Value 0xFFFF Counter cleared by compare match with RC Counter cleared by trigger RC RB RA Waveform Examples Time TIOB TIOA 28.6.3.4 WAVSEL = 1 When CMRn.WAVSEL is one, the value of CVn is incremented from 0 to 0xFFFF.
AT32UC3A3 A trigger such as an external event or a software trigger can modify CVn at any time. If a trigger occurs while CVn is incrementing, CVn then decrements. If a trigger is received while CVn is decrementing, CVn then increments. See Figure 28-11 on page 762. RC Compare cannot be programmed to generate a trigger in this configuration. At the same time, RC Compare can stop the counter clock (CMRn.CPCSTOP = 1) and/or disable the counter clock (CMRn.CPCDIS = 1). Figure 28-10.
AT32UC3A3 28.6.3.5 WAVSEL = 3 When CMRn.WAVSEL is three, the value of CVn is incremented from zero to RC. Once RC is reached, the value of CVn is decremented to zero, then re-incremented to RC and so on. See Figure 28-12 on page 763. A trigger such as an external event or a software trigger can modify CVn at any time. If a trigger occurs while CVn is incrementing, CVn then decrements. If a trigger is received while CVn is decrementing, CVn then increments. See Figure 28-13 on page 764.
AT32UC3A3 Figure 28-13. WAVSEL = 3 With Trigger Counter Value 0xFFFF Counter decremented by compare match with RC RC Counter decremented by trigger RB Counter incremented by trigger RA Waveform Examples TIOB Time TIOA 28.6.3.6 External event/trigger conditions An external event can be programmed to be detected on one of the clock sources (XC0, XC1, XC2) or TIOB. The external event selected can then be used as a trigger. The External Event Selection field in CMRn (CMRn.
AT32UC3A3 • RB Compare Effect on TIOB (CMRn.BCPB) • RC Compare Effect on TIOA (CMRn.ACPC) • RA Compare Effect on TIOA (CMRn.
AT32UC3A3 28.7 User Interface Table 28-3.
AT32UC3A3 Notes: 1. Read-only if CMRn.WAVE is zero. 2. The reset values are device specific. Please refer to the Module Configuration section at the end of this chapter.
AT32UC3A3 28.7.1 Name: Channel Control Register CCR Access Type: Write-only Offset: 0x00 + n * 0x40 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - SWTRG CLKDIS CLKEN • SWTRG: Software Trigger Command 1: Writing a one to this bit will perform a software trigger: the counter is reset and the clock is started.
AT32UC3A3 28.7.
AT32UC3A3 0: TIOB is used as an external trigger. • ETRGEDG: External Trigger Edge Selection ETRGEDG Edge 0 none 1 rising edge 2 falling edge 3 each edge • LDBDIS: Counter Clock Disable with RB Loading 1: Counter clock is disabled when RB loading occurs. 0: Counter clock is not disabled when RB loading occurs. • LDBSTOP: Counter Clock Stopped with RB Loading 1: Counter clock is stopped when RB loading occurs. 0: Counter clock is not stopped when RB loading occurs.
AT32UC3A3 28.7.
AT32UC3A3 • BCPC: RC Compare Effect on TIOB BCPC Effect 0 none 1 set 2 clear 3 toggle • BCPB: RB Compare Effect on TIOB BCPB Effect 0 none 1 set 2 clear 3 toggle • ASWTRG: Software Trigger Effect on TIOA ASWTRG Effect 0 none 1 set 2 clear 3 toggle • AEEVT: External Event Effect on TIOA AEEVT Effect 0 none 1 set 2 clear 3 toggle • ACPC: RC Compare Effect on TIOA ACPC Effect 0 none 1 set 2 clear 3 toggle 772 32072H–AVR32–10/2012
AT32UC3A3 • ACPA: RA Compare Effect on TIOA ACPA Effect 0 none 1 set 2 clear 3 toggle • WAVE 1: Waveform mode is enabled. 0: Waveform mode is disabled (Capture mode is enabled).
AT32UC3A3 • CPCSTOP: Counter Clock Stopped with RC Compare 1: Counter clock is stopped when counter reaches RC. 0: Counter clock is not stopped when counter reaches RC. • BURST: Burst Signal Selection BURST Burst Signal Selection 0 The clock is not gated by an external signal. 1 XC0 is ANDed with the selected clock. 2 XC1 is ANDed with the selected clock. 3 XC2 is ANDed with the selected clock. • CLKI: Clock Invert 1: Counter is incremented on falling edge of the clock.
AT32UC3A3 28.7.4 Name: Channel Counter Value Register CV Access Type: Read-only Offset: 0x10 + n * 0x40 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 3 2 1 0 CV[15:8] 7 6 5 4 CV[7:0] • CV: Counter Value CV contains the counter value in real time.
AT32UC3A3 28.7.5 Name: Channel Register A RA Access Type: Read-only if CMRn.WAVE = 0, Read/Write if CMRn.WAVE = 1 Offset: 0x14 + n * 0X40 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 3 2 1 0 RA[15:8] 7 6 5 4 RA[7:0] • RA: Register A RA contains the Register A value in real time.
AT32UC3A3 28.7.6 Name: Channel Register B RB Access Type: Read-only if CMRn.WAVE = 0, Read/Write if CMRn.WAVE = 1 Offset: 0x18 + n * 0x40 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 3 2 1 0 RB[15:8] 7 6 5 4 RB[7:0] • RB: Register B RB contains the Register B value in real time.
AT32UC3A3 28.7.7 Name: Channel Register C RC Access Type: Read/Write Offset: 0x1C + n * 0x40 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 3 2 1 0 RC[15:8] 7 6 5 4 RC[7:0] • RC: Register C RC contains the Register C value in real time.
AT32UC3A3 28.7.8 Name: Channel Status Register SR Access Type: Read-only Offset: 0x20 + n * 0x40 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - MTIOB MTIOA CLKSTA 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS Note: Reading the Status Register will also clear the interrupt bit for the corresponding interrupts.
AT32UC3A3 • CPBS: RB Compare Status 1: This bit is set when an RB Compare has occurred and CMRn.WAVE is one. 0: This bit is cleared when the SR register is read. • CPAS: RA Compare Status 1: This bit is set when an RA Compare has occurred and CMRn.WAVE is one. 0: This bit is cleared when the SR register is read. • LOVRS: Load Overrun Status 1: This bit is set when RA or RB have been loaded at least twice without any read of the corresponding register and CMRn.WAVE is zero.
AT32UC3A3 28.7.9 Name: Channel Interrupt Enable Register IER Access Type: Write-only Offset: 0x24 + n * 0x40 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS Writing a zero to a bit in this register has no effect.
AT32UC3A3 28.7.10 Name: Channel Interrupt Disable Register IDR Access Type: Write-only Offset: 0x28 + n * 0x40 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS Writing a zero to a bit in this register has no effect.
AT32UC3A3 28.7.11 Name: Channel Interrupt Mask Register IMR Access Type: Read-only Offset: 0x2C + n * 0x40 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled.
AT32UC3A3 28.7.12 Name: Block Control Register BCR Access Type: Write-only Offset: 0xC0 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - SYNC • SYNC: Synchro Command 1: Writing a one to this bit asserts the SYNC signal which generates a software trigger simultaneously for each of the channels.
AT32UC3A3 28.7.
AT32UC3A3 • TC0XC0S: External Clock Signal 0 Selection TC0XC0S Signal Connected to XC0 0 TCLK0 1 none 2 TIOA1 3 TIOA2 786 32072H–AVR32–10/2012
AT32UC3A3 28.7.14 Name: Features Register FEATURES Access Type: Read-only Offset: 0xF8 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - BRPBHSB UPDNIMPL 7 6 5 4 3 2 1 0 CTRSIZE • BRPBHSB: Bridge type is PB to HSB 1: Bridge type is PB to HSB. 0: Bridge type is not PB to HSB. • UPDNIMPL: Up/down is implemented 1: Up/down counter capability is implemented.
AT32UC3A3 28.7.15 Name: Version Register VERSION Access Type: Read-only Offset: 0xFC Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated.
AT32UC3A3 28.8 Module Configuration The specific configuration for each TC instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks according to the table in the Power Manager section. Table 28-4. 28.8.1 Module Clock Name Module name Clock name TC0 CLK_TC0 TC1 CLK_TC1 Clock Connections Each Timer/Counter channel can independently select an internal or external clock source for its counter: Table 28-5.
AT32UC3A3 29. Analog-to-Digital Converter (ADC) Rev: 2.0.0.1 29.
AT32UC3A3 29.3 Block Diagram Figure 29-1. ADC Block Diagram Timer Counter Channels ADC Trigger Selection TRIGGER Control Logic ADC Interrupt Interrupt Controller VDDANA VREF ADDedicated Analog Inputs Peripheral DMA Controller AD- AD- Analog Inputs Multiplexed With I/O lines ADAD- I/O Controller Successive Approximation Register Analog-to-Digital Converter User Interface High Speed Bus (HSB) Peripheral Bridge Peripheral Bus (PB) AD- GND 29.4 I/O Lines Description Table 29-1.
AT32UC3A3 29.5.2 Power Management In sleep mode, the ADC clock is automatically stopped after each conversion. As the logic is small and the ADC cell can be put into sleep mode, the Power Manager has no effect on the ADC behavior. 29.5.3 Clocks The clock for the ADC bus interface (CLK_ADC) is generated by the Power Manager. This clock is enabled at reset, and can be disabled in the Power Manager.
AT32UC3A3 as zero. The two highest bits of the Last Data Converted field in the Last Converted Data Register (LCDR.LDATA) will be read as zero too. Moreover, when a Peripheral DMA channel is connected to the ADC, a 10-bit resolution sets the transfer request size to 16-bit. Writing a one to the LOWRES bit automatically switches to 8-bit data transfers. In this case, the destination buffers are optimized. 29.6.
AT32UC3A3 If the CDR register is not read before further incoming data is converted, the corresponding Overrun Error bit in the SR register (SR.OVREn) is set. In the same way, new data converted when DRDY is high sets the General Overrun Error bit in the SR register (SR.GOVRE). The OVREn and GOVRE bits are automatically cleared when the SR register is read. Figure 29-3.
AT32UC3A3 29.6.5 Conversion Triggers Conversions of the active analog channels are started with a software or a hardware trigger. The software trigger is provided by writing a one to the START bit in the Control Register (CR.START). The hardware trigger can be one of the TIOA outputs of the Timer Counter channels, or the external trigger input of the ADC (TRIGGER). The hardware trigger is selected with the Trigger Selection field in the Mode Register (MR.TRIGSEL).
AT32UC3A3 29.6.7 ADC Timings Each ADC has its own minimal startup time that is defined through the Start Up Time field in the Mode Register (MR.STARTUP). This startup time is given in the Electrical Characteristics chapter. In the same way, a minimal sample and hold time is necessary for the ADC to guarantee the best converted final value between two channels selection. This time has to be defined through the Sample and Hold Time field in the Mode Register (MR.SHTIM).
AT32UC3A3 29.7 User Interface Table 29-2.
AT32UC3A3 29.7.1 Name: Control Register CR Access Type: Write-only Offset: 0x00 Reset Value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 START 0 SWRST • START: Start Conversion Writing a one to this bit will begin an analog-to-digital conversion. Writing a zero to this bit has no effect. This bit always reads zero.
AT32UC3A3 29.7.2 Name: Mode Register MR Access Type: Read/Write Offset: 0x04 Reset Value: 0x00000000 31 – 30 – 29 – 28 – 27 23 – 22 21 20 19 STARTUP 15 14 13 12 26 25 24 18 17 16 11 10 9 8 3 2 TRGSEL 1 0 TRGEN SHTIM PRESCAL 7 – 6 – 5 SLEEP 4 LOWRES • SHTIM: Sample & Hold Time Sample & Hold Time = (SHTIM+3) / ADCClock • STARTUP: Start Up Time Startup Time = (STARTUP+1) * 8 / ADCClock This Time should respect a minimal value.
AT32UC3A3 29.7.3 Name: Channel Enable Register CHER Access Type: Write-only Offset: 0x10 Reset Value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 CH7 6 CH6 5 CH5 4 CH4 3 CH3 2 CH2 1 CH1 0 CH0 • CHn: Channel n Enable Writing a one to these bits will set the corresponding bit in CHSR. Writing a zero to these bits has no effect. These bits always read a zero.
AT32UC3A3 29.7.4 Name: Channel Disable Register CHDR Access Type: Write-only Offset: 0x14 Reset Value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 CH7 6 CH6 5 CH5 4 CH4 3 CH3 2 CH2 1 CH1 0 CH0 • CHn: Channel n Disable Writing a one to these bits will clear the corresponding bit in CHSR. Writing a zero to these bits has no effect. These bits always read a zero.
AT32UC3A3 29.7.5 Name: Channel Status Register CHSR Access Type: Read-only Offset: 0x18 Reset Value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 CH7 6 CH6 5 CH5 4 CH4 3 CH3 2 CH2 1 CH1 0 CH0 • CHn: Channel n Status These bits are set when the corresponding bits in CHER is written to one. These bits are cleared when the corresponding bits in CHDR is written to one.
AT32UC3A3 29.7.6 Name: Status Register SR Access Type: Read-only Offset: 0x1C Reset Value: 0x000C0000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 RXBUFF 18 ENDRX 17 GOVRE 16 DRDY 15 OVRE7 14 OVRE6 13 OVRE5 12 OVRE4 11 OVRE3 10 OVRE2 9 OVRE1 8 OVRE0 7 EOC7 6 EOC6 5 EOC5 4 EOC4 3 EOC3 2 EOC2 1 EOC1 0 EOC0 • RXBUFF: RX Buffer Full This bit is set when the Buffer Full signal from the Peripheral DMA is active.
AT32UC3A3 29.7.7 Name: Last Converted Data Register LCDR Access Type: Read-only Offset: 0x20 Reset Value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 7 6 5 4 3 2 1 8 LDATA[9:8] 0 LDATA[7:0] • LDATA: Last Data Converted The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion is completed.
AT32UC3A3 29.7.8 Name: Interrupt Enable Register IER Access Type: Write-only Offset: 0x24 Reset Value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 RXBUFF 18 ENDRX 17 GOVRE 16 DRDY 15 OVRE7 14 OVRE6 13 OVRE5 12 OVRE4 11 OVRE3 10 OVRE2 9 OVRE1 8 OVRE0 7 EOC7 6 EOC6 5 EOC5 4 EOC4 3 EOC3 2 EOC2 1 EOC1 0 EOC0 Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR.
AT32UC3A3 29.7.9 Name: Interrupt Disable Register IDR Access Type: Write-only Offset: 0x28 Reset Value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 RXBUFF 18 ENDRX 17 GOVRE 16 DRDY 15 OVRE7 14 OVRE6 13 OVRE5 12 OVRE4 11 OVRE3 10 OVRE2 9 OVRE1 8 OVRE0 7 EOC7 6 EOC6 5 EOC5 4 EOC4 3 EOC3 2 EOC2 1 EOC1 0 EOC0 Writing a zero to a bit in this register has no effect.
AT32UC3A3 29.7.10 Name: Interrupt Mask Register IMR Access Type: Read-only Offset: 0x2C Reset Value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 RXBUFF 18 ENDRX 17 GOVRE 16 DRDY 15 OVRE7 14 OVRE6 13 OVRE5 12 OVRE4 11 OVRE3 10 OVRE2 9 OVRE1 8 OVRE0 7 EOC7 6 EOC6 5 EOC5 4 EOC4 3 EOC3 2 EOC2 1 EOC1 0 EOC0 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled.
AT32UC3A3 29.7.11 Name: Channel Data Register CDRx Access Type: Read-only Offset: 0x2C-0x4C Reset Value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 7 6 5 4 3 2 1 8 DATA[9:8] 0 DATA[7:0] • DATA: Converted Data The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion is completed.
AT32UC3A3 29.7.12 Name: Version Register VERSION Access Type: Read-only Offset: 0xFC Reset Value: – 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 18 17 16 15 – 14 – 13 – 12 – 11 10 9 VERSION[11:8] 8 7 6 5 4 3 2 0 VARIANT 1 VERSION[7:0] • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated.
AT32UC3A3 29.8 Module Configuration The specific configuration for the ADC instance is listed in the following tables. Table 29-3.
AT32UC3A3 30. HSB Bus Performance Monitor (BUSMON) Rev 1.0.0.0 30.1 Features • Allows performance monitoring of High Speed Bus master interfaces – Up to 4 masters can be monitored – Peripheral Bus access to monitor registers • The following is monitored – Data transfer cycles – Bus stall cycles – Maximum access latency for a single transfer • Automatic handling of event overflow 30.2 Overview BUSMON allows the user to measure the activity and stall cycles on the High Speed Bus (HSB).
AT32UC3A3 30.4 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 30.4.1 Clocks The clock for the BUSMON bus interface (CLK_BUSMON) is generated by the Power Manager. This clock is enabled at reset and can be disabled in the Power Manager. It is recommended to disable the BUSMON before disabling the clock, to avoid freezing the BUSMON in an undefined state. 30.
AT32UC3A3 30.6 User interface Table 30-1.
AT32UC3A3 30.6.1 Name: Control Register CONTROL Access Type: Read/Write Offset: 0x00 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - CH3RES CH2RES CH1RES CH0RES 15 14 13 12 11 10 9 8 - - - - CH3OF CH2OF CH1OF CH0OF 7 6 5 4 3 2 1 0 - - - - CH3EN CH2EN CH1EN CH0EN • CHnRES: Channel Counter Reset Writting a one to this bit will reset the counter in the channel n.
AT32UC3A3 30.6.2 Name: Channel n Data Cycles Register DATAn Access Type: Read-Only Offset: 0x10 + n*0x10 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 DATA[31:24] 23 22 21 20 DATA[23:16] 15 14 13 12 DATA[15:8] 7 6 5 4 DATA[7:0] • DATA: Data cycles counted since the last reset.
AT32UC3A3 30.6.3 Name: Channel n Stall Cycles Register STALLn Access Type: Read-Only Offset: 0x14 + n*0x10 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 STALL[31:24] 23 22 21 20 STALL[23:16] 15 14 13 12 STALL[15:8] 7 6 5 4 STALL[7:0] • STALL: Stall cycles counted since the last reset.
AT32UC3A3 30.6.4 Name: Channel n Max Transfer Initiation Cycles Register LATn Access Type: Read-Only Offset: 0x18 + n*0x10 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 LAT[31:24] 23 22 21 20 LAT[23:16] 15 14 13 12 LAT[15:8] 7 6 5 4 LAT[7:0] • LAT: This field is cleared whenever the DATA or STALL register is reset. Maximum transfer initiation cycles counted since the last reset. This counter is saturating.
AT32UC3A3 30.6.5 Name: Parameter Register PARAMETER Access Type: Read-only Offset: 0x50 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - CH3IMPL CH2IMPL CH1IMPL CH0IMPL • CHnIMP: Channel Implementation 1: The corresponding channel is implemented. 0: The corresponding channel is not implemented.
AT32UC3A3 30.6.6 Name: Version Register VERSION Access Type: Read-only Offset: 0x54 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated.
AT32UC3A3 30.7 Module Configuration Table 30-2.
AT32UC3A3 31. MultiMedia Card Interface (MCI) Rev. 4.1.0.0 31.1 Features • • • • • • • • • • • • • • 31.2 Compatible with Multimedia Card specification version 4.3 Compatible with SD Memory Card specification version 2.0 Compatible with SDIO specification version 1.1 Compatible with CE-ATA specification 1.
AT32UC3A3 31.3 Block Diagram Figure 31-1. MCI Block Diagram Peripheral Bus Brigde DMA Controller Peripheral Bus CLK CMD I/O controller MCI Interface Power Manager DATA CLK_MCI Interrupt Control MCI Interrupt Figure 31-2.
AT32UC3A3 31.4 I/O Lines Description Table 31-1. I/O Lines Description Pin Name Pin Description Type (1) Comments CMD[1:0] Command/Response Input/Output/ PP/OD CMD of a MMC or SDCard/SDIO CLK Clock Input/Output CLK of a MMC or SD Card/SDIO DATA[7:0] Data 0..7 of Slot A Input/Output/PP DAT[0..7] of a MMC DAT[0..3] of a SD Card/SDIO DATA[15:8] Data 0..7 of Slot B Input/Output/PP DAT[0..7] of a MMC DAT[0..3] of a SD Card/SDIO 1. PP: Push/Pull, OD: Open Drain 31.
AT32UC3A3 The MultiMedia Card communication is based on a 13-pin serial bus interface. It has three communication lines and four supply lines. Table 31-2.
AT32UC3A3 The SD Memory Card bus includes the signals listed in Table 31-3 on page 825. Table 31-3.
AT32UC3A3 Figure 31-8. Mixing MultiMedia and SD Memory Cards with Two Slots DATA[7:0] CMD[0] CLK CLK 12 34567 91011 1213 8 91011 1213 8 91011 1213 8 MMC1 MMC2 MMC3 SDCARD 9 CMD[1] 12 34567 12 345 678 DATA[11:8] 12 34567 When the MCI is configured to operate with SD memory cards, the width of the data bus can be selected in the SDCard /SDIO Bus Width field in the SDCR register (SDCR.SDCBUS). See Section “31.7.4” on page 847. for details.
AT32UC3A3 The structure of commands, responses and data blocks is described in the MultiMedia-Card System Specification. Refer also to Table 31-5 on page 828. MultiMediaCard bus data transfers are composed of these tokens. There are different types of operations. Addressed operations always contain a command and a response token. In addition, some operations have a data token; the others transfer their information directly within the command or response structure.
AT32UC3A3 The command ALL_SEND_CID and the fields and values for CMDR register are described in Table 31-5 on page 828 and Table 31-6 on page 828. Table 31-5. CMD Index CMD2 Note: ALL_SEND_CID Command Description Type bcr Argument [31:0] stuff bits Resp R2 Abbreviation ALL_SEND_CID Command Description Asks all cards to send their CID numbers on the CMD line bcr means broadcast command with response. Table 31-6.
AT32UC3A3 Figure 31-9. Command/Response Functional Flow Diagram Set the command argument ARGR = Argument(1) Set the command CMD = Command Read the SR register Wait for SR.CMDRY bit set to one 0 SR.CMDRDY 1 Check error bits in the SR register(1) Yes Status error bits? Read response if required RETURN ERROR(1) RETURN OK Note: 31.6.3 1. If the command is SEND_OP_COND, the CRC error bit is always present (refer to R3 response in the MultiMedia Card specification).
AT32UC3A3 Consequent to MMC Specification 3.1, two types of multiple block read (or write) transactions are defined (the host can use either one at any time): • Open-ended/Infinite Multiple block read (or write): The number of blocks for the read (or write) multiple block operation is not defined. The card will continuously transfer (or program) data blocks until a stop transmission command is received. • Multiple block read (or write) with pre-defined block count (since version 3.
AT32UC3A3 Figure 31-10. Read Functional Flow Diagram Send SELECT/DESELECT_CARD Command(1) to select the card Send SET_BLOCKLEN command(1) No Read with DMA Write a zero in the DMA.DMAEN bit Write the BlockLenght in the MR.BLKLEN field(2) Write the block count in the BLKR.BCNT field (if necessary) Yes Write a one in the DMA.DMAEN bit Write the BlockLenght in the MR.BLKLEN field(2) Configure the DMA channel X write the Data Adress in the DMA Controller write the (MR.
AT32UC3A3 In write operation, the Padding Value bit in the MR register (MR.PADV) is used to define the padding value when writing non-multiple block size. When the MR.PADV is zero, then 0x00 value is used when padding data, otherwise 0xFF is used. Write a one in the DMA Hardware Handshaking Enable bit in the DMA Configuration Register (DMA.DMAEN) enables DMA transfer. The following flowchart shows how to write a single block with or without use of DMA facilities (see Figure 31-11 on page 833).
AT32UC3A3 Figure 31-11. Write Functional Flow Diagram Send SELECT/DESELECT_CARD Command(1) to select the card Send SET_BLOCKLEN command(1) No Write using DMA Write a zero in the DMA.DMAEN bit Write the BlockLenght in the MR.BLKLEN field(2) Write the block count in the BLKR.BCNT field (if necessary) Yes Write a one in the DMA.DMAEN bit Write the BlockLenght in the MR.BLKLEN field(2) Configure the DMA channel X write the Data Adress in the DMA Controller write the (MR.
AT32UC3A3 The following flowchart shows how to manage a multiple write block transfer with the DMA Controller (see Figure 31-12 on page 835). Polling or interrupt method can be used to wait for the end of write according to the contents of the IMR register.
AT32UC3A3 Figure 31-12. Multiple Write Functional Flow Diagram Send SELECT/DESELECT_CARD Command(1) to select the card Send SET_BLOCKLEN command(1) Write a zero in the DMA.DMAEN bit Write the block lenght in the MR.BLKLEN field(2) Write the block count in the BLKR.BCNT field (if necessary) Configure the DMA channel X write the Data Adress in the DMA Controller write the (MR.
AT32UC3A3 31.6.4.1 WRITE_SINGLE_BLOCK operation using DMA Controller 1. Wait until the current command execution has successfully terminated. c. Check that the Transfer Done bit in the SR register (SR.XFRDONE) is set 2. Write the block length in the card. This value defines the value block_lenght. 3. Write the MR.BLKLEN with block_lenght value. 4. Configure the DMA Channel in the DMA Controller. 5.
AT32UC3A3 31.6.4.4 READ_MULTIPLE_BLOCK 1. Wait until the current command execution has successfully terminated. a. Check that the SR.CMDRDY and the SR.NOTBUSY are set. 2. Write the block length in the card. This value defines the value block_lenght. 3. Write the MR.BLKLEN with block_lenght value. 4. Program the DMA Controller to use a list of descriptors. 5. Write the DMA register with the following fields: – Write zero to the DMA.OFFSET. – Write the DMA.CHKSIZE. – Write a one to the DMA.
AT32UC3A3 An SDIO Card can have multiple I/O or combined I/O and memory (called Combo Card). Within a multi-function SDIO or a Combo card, there are multiple devices (I/O and memory) that share access to the SD bus. In order to allow the sharing of access to the host among multiple devices, SDIO and combo cards can implement the optional concept of suspend/resume (Refer to the SDIO Specification for more details).
AT32UC3A3 CMDR register (CMDR.SPCMD) must be set to three to issue the CE-ATA completion Signal Disable Command. 31.6.6.4 CE-ATA Error Recovery Several methods of ATA command failure may occur, including: • No response to an MMC command, such as RW_MULTIPLE_REGISTER (CMD60). • CRC is invalid for an MMC command or response. • CRC16 is invalid for an MMC data packet. • ATA Status register reflects an error by setting the ERR bit to one.
AT32UC3A3 6. When Data transfer is completed, host processor shall terminate the boot stream by writing the MCI_CMDR register with SPCMD field set to BOOTEND. 31.6.7.2 Boot Procedure, dma mode 1. Configure MCI2 data bus width programming SDCBUS Field in the MCI_SDCR register. The BOOT_BUS_WIDTH field in the device Extended CSD register must be set accordingly. 2. Set the bytecount to 512 bytes and the blockcount to the desired number of block, writing BLKLEN and BCNT fields of the MCI_BLKR Register. 3.
AT32UC3A3 31.6.8.3 Write Access During a write access, the SR.XFRDONE bit behaves as shown in Figure 31-14 on page 841. Figure 31-14. SR.XFRDONE During a Write Access CMD line MCI writeCMD Card response The CMDRDY flag is released 8 tbit lafter the end of the card response. CMDRDY flag D0 is tied by the card D0 is released D0 1st Block Last Block 1st Block Last Block Data bus - D0 Not busy flag XFRDONE flag 31.7 User Interface Table 31-7.
AT32UC3A3 Table 31-7. 1.
AT32UC3A3 31.7.1 Name: Control Register CR Access Type: Write-only Offset: 0x000 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 SWRST - IOWAITDIS IOWAITEN PWSDIS PWSEN MCIDIS MCIEN • SWRST: Software Reset Writing a one to this bit will reset the MCI interface. Writing a zero to this bit has no effect.
AT32UC3A3 31.7.2 Name: Mode Register MR Access Type: Read-write Offset: 0x004 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 10 9 8 BLKLEN[15:8] 23 22 21 20 BLKLEN[7:0] 15 14 13 12 11 - PADV FBYTE WRPROOF RDPROOF 7 6 5 4 3 PWSDIV 2 1 0 CLKDIV • BLKLEN[15:0]: Data Block Length This field determines the size of the data block. This field is also accessible in the BLKR register.
AT32UC3A3 • PWSDIV: Power Saving Divider Multimedia Card Interface clock is divided by 2(PWSDIV) + 1 when entering Power Saving Mode. Warning: This value must be different from zero before enabling the Power Save Mode in the CR register (CR.PWSEN). • CLKDIV: Clock Divider The Multimedia Card Interface Clock (CLK) is CLK_MCI divided by (2*(CLKDIV+1)).
AT32UC3A3 31.7.3 Name: Data Time-out Register DTOR Access Type: Read/Write Offset: 0x008 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - DTOMUL DTOCYC These two fields determine the maximum number of CLK_MCI cycles that the MCI waits between two data block transfers. It is equal to (DTOCYC x Multiplier).
AT32UC3A3 31.7.4 Name: SDCard/SDIO Register SDCR Access Type: Read/Write Offset: 0x00C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 – – – – SDCBUS SDCSEL • SDCBUS: SDCard/SDIO Bus Width SDCBUS BUS WIDTH 0 1 bit 1 Reserved 2 4 bits 3 8 bits • SDCSEL: SDCard/SDIO Slot SDCSEL SDCard/SDIO Slot 0 Slot A is selected.
AT32UC3A3 31.7.5 Name: Argument Register ARGR Access Type: Read/Write Offset: 0x010 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ARG[31:24] 23 22 21 20 ARG[23:16] 15 14 13 12 ARG[15:8] 7 6 5 4 ARG[7:0] • ARG[31:0]: Command Argument this field contains the argument field of the command.
AT32UC3A3 31.7.6 Name: Command Register CMDR Access Type: Write-only Offset: 0x014 Reset Value: 0x00000000 31 30 29 28 27 26 - - - - BOOTACK ATACS 23 22 21 20 19 18 - - 15 14 13 12 11 - - - MAXLAT OPDCMD 7 6 5 4 3 TRTYP RSPTYP 25 24 IOSPCMD 17 TRDIR 10 16 TRCMD 9 8 SPCMD 2 1 0 CMDNB This register is write-protected while SR.CMDRDY is zero. If an interrupt command is sent, this register is only writable by an interrupt response (SPCMD field).
AT32UC3A3 • TRTYP: Transfer Type TRTYP Transfer Type 0 MMC/SDCard Single Block 1 MMC/SDCard Multiple Block 2 MMC Stream 3 Reserved 4 SDIO Byte 5 SDIO Block others Reserved • TRDIR: Transfer Direction Writing a zero to this bit will configure the transfer direction as write transfer. Writing a one to this bit will configure the transfer direction as read transfer.
AT32UC3A3 • RSPTYP: Response Type RSP Response Type 0 No response. 1 48-bit response. 2 136-bit response. 3 R1b response type • CMDNB: Command Number The Command Number to transmit.
AT32UC3A3 31.7.7 Name: Block Register BLKR Access Type: Read/Write Offset: 0x018 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 BLKLEN[15:8] 23 22 21 20 BLKLEN[7:0] 15 14 13 12 BCNT[15:8] 7 6 5 4 BCNT[7:0] • BLKLEN: Data Block Length This field determines the size of the data block. This field is also accessible in the MR register. If MR.FBYTE bit is zero, the BLKEN[17:16] field must be written to 0b00 Notes: 1.
AT32UC3A3 31.7.8 Name: Completion Signal Time-out Register CSTOR Access Type: Read-write Offset: 0x01C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - CSTOMUL CSTOCYC These two fields determines the maximum number of CLK_MCI cycles that the MCI waits between two data block transfers.
AT32UC3A3 31.7.9 Name: Response Register n RSPRn Access Type: Read-only Offset: 0x020 + 0*0x04 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RSP[31:24] 23 22 21 20 RSP[23:16] 15 14 13 12 RSP[15:8] 7 6 5 4 RSP[7:0] • RSP[31:0]: Response The response register can be read by N access(es) at the same RSPRn or at consecutive addresses (0x20 + n*0x04). N depends on the size of the response.
AT32UC3A3 31.7.10 Name: Receive Data Register RDR Access Type: Read-only Offset: 0x030 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 DATA[31:24] 23 22 21 20 DATA[23:16] 15 14 13 12 DATA[15:8] 7 6 5 4 DATA[7:0] • DATA[31:0]: Data to Read The last data received.
AT32UC3A3 31.7.11 Name: Transmit Data Register TDR Access Type: Write-only Offset: 0x034 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 DATA[31:24] 23 22 21 20 DATA[23:16] 15 14 13 12 DATA[15:8] 7 6 5 4 DATA[7:0] • DATA[31:0]: Data to Write The data to send.
AT32UC3A3 31.7.
AT32UC3A3 • CSTOE: Completion Signal Time-out Error This bit is set when the completion signal time-out defined by the CSTOR.CSTOCYC field and the CSTOR.CSTOMUL field is reached. This bit is cleared when reading the SR register. • DTOE: Data Time-out Error This bit is set when the data time-out defined by the DTOR.DTOCYC field and the DTOR.DTOMUL field is reached. This bit is cleared when reading the SR register. • DCRCE: Data CRC Error This bit is set when a CRC16 error is detected in the last data block.
AT32UC3A3 • • • • • A block write operation uses a simple busy signalling of the write operation duration on the data (DAT[0]) line: during a data transfer block, if the card does not have a free data receive buffer, the card indicates this condition by pulling down the data line (DAT[0]) to LOW. The card stops pulling down the data line as soon as at least one receive buffer for the defined data transfer block length becomes free. The NOTBUSY bit allows to deal with these different states.
AT32UC3A3 31.7.
AT32UC3A3 31.7.
AT32UC3A3 31.7.
AT32UC3A3 31.7.16 Name: DMA Configuration Register DMA Access Type: Read/Write Offset: 0x050 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - DAMEN 7 6 5 4 3 2 1 0 - - - CHKSIZE OFFSET • DMAEN: DMA Hardware Handshaking Enable 1: DMA Interface is enabled. 0: DMA interface is disabled.
AT32UC3A3 31.7.17 Name: Configuration Register CFG Access Type: Read/Write Offset: 0x054 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - LSYNC - - - HSMODE 7 6 5 4 3 2 1 0 - - - FERRCTRL - - - FIFOMODE • LSYNC: Synchronize on the last block 1: The pending command is sent at the end of the block transfer when the transfer length is not infinite.
AT32UC3A3 31.7.18 Name: Write Protect Mode Register WPMR Access Type: Read/Write Offset: 0x0E4 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 WPKEY[23:16] 23 22 21 20 WPKEY[15:8] 15 14 13 12 WPKEY[7:0] 7 6 5 4 3 2 1 0 - - - - - - - WPEN • WPKEY[23:0]: Write Protection Key password This field should be written at value 0x4D4349 (ASCII code for “MCI”). Writing any other value in this field has no effect.
AT32UC3A3 31.7.19 Name: Write Protect Status Register WPSR Access Type: Read-only Offset: 0x0E8 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 10 9 8 2 1 0 WPVSRC[15:8] 15 14 13 12 11 WPVSRC[7:0] 7 6 5 4 - - - - 3 WPVS • WPVSRC[15:0]: Write Protection Violation Source This field contains address where the violation access occurs.
AT32UC3A3 31.7.20 Name: Version Register VERSION Access: Read-only Offset: 0x0FC Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - 15 14 13 12 11 - - - - 7 6 5 4 VARIANT 10 9 8 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module.
AT32UC3A3 31.7.
AT32UC3A3 31.8 Module Configuration The specific configuration for the MCI instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks according to the table in the Power Manager section. Table 31-8. Module Clock Name Module name Clock name MCI CLK_MCI Table 31-9. Parameter Value Name Value FIFO_SIZE 128 Table 31-10.
AT32UC3A3 32. Memory Stick Interface (MSI) Rev: 2.1.0.0 32.1 Features • • • • • • 32.2 Memory Stick ver. 1.x & Memory Stick PRO support Memory Stick serial clock (serial mode: 20 MHz max., parallel mode: 40 MHz max.) Data transmit/receive FIFO of 64 bits x 4 16 bits CRC circuit DMACA transfer support Card insertion/removal detection Overview The Memory Stick Interface (MSI) is a host controller that supports Memory Stick Version 1.X and Memory Stick PRO.
AT32UC3A3 Figure 32-2. Write packet BS BS0 BS1 BS2 Memory Stick SDIO / DATA[3:0] INT BS3 Host TPC DATA BS0 Memory Stick CRC RDY/BSY INT SCLK 32.3 Block Diagram Figure 32-3. MSI block diagram CLK_MSI INS ÷ Registers PB SDIO / DATA0 DATA1 FIFO 64 x 4 DATA2 DATA3 MS I/F SCLK BS 32.4 32.4.1 Data buffer Product Dependencies GPIO SCLK, DATA[3..0], BS & INS are I/O lines, multiplexed with other I/O lines. The I/O controller must be configured so that MSI can drive these I/O lines.
AT32UC3A3 32.4.3 Interrupt Controller MSI interrupt line is connected to the Interrupt Controller. In order to handle interrupts, Interrupt Controller(INTC) must be programmed before configuring MSI. 32.4.4 DMA Controller (DMACA) Handshake signals are connected to DMACA. In order to accelerate transfer from/to flash card, DMACA must be programmed before using MSI. 32.
AT32UC3A3 32.6 32.6.1 Functional Description Reset Operation An internal reset (initialization of the internal registers and operating sequence) is performed when PB reset is active or by setting SYS.RST=1. RST bit is cleared to 0 after the internal reset is completed. The protocol currently being executed stops, and the internal operating sequence is initialized. In addition, the FIFO is set to the empty state (SR.EMP=1, SR.FUL=0).
AT32UC3A3 sources can be cleared by setting corresponding bit in ISCR but DRQ which is cleared once FIFO has been read/written. Figure 32-5. Communication example CPU Interrupt enable FIFO direction setting Write to FIFO TPC setting MSI PEND=1, MSINT=1 FDIR=1 CMD TPC = SET_CMD Interrupt wait MSIER register MSSYS register MSDAT register MSCMD register Protocol start Communication with Memory Stick MSISR.
AT32UC3A3 Figure 32-6. Interface mode switching sequence Serial Interface Mode (MSSYS.SRAC=1, MSSYS.REI=1) SET_R/W_REG_ADRS TPC WRITE_REG TPC system parameter (PAM bit) Error OK Set Parallel Interface Mode (MSSYS.SRAC=0, MSSYS.REI=0) Change SCLK (MSSYS.CLKDIV[7:0]=X) 32.6.
AT32UC3A3 the interrupt source, even if the interrupt is masked, can be read in ISR. DRQ interrupt request is cleared by reading (reception) or writing (transmission) FIFO, other interrupt requests are cleared by writing 1 to the corresponding bit in Interrupt Status Clear Register (ISCR). 32.6.6 OCD mode There is no OCD mode for MSI. 32.7 User Interface Table 32-2.
AT32UC3A3 32.7.1 Name : Command register CMD Access Type : Read/Write Offset : 0x00 Reset Value : 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - DSL 3 2 TPC 7 6 5 4 DSZ 1 0 DSZ • TPC : Transfer Protocol Code.
AT32UC3A3 1 : Reserved. • DSZ : Data size. Length can be set from 1 byte to 1024 bytes. However, 1024 bytes is set when DSZ=0.
AT32UC3A3 32.7.2 Name : Data register DAT Access Type : Read/Write Offset : 0x04 Reset Value : 0x4C004C00 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 DATA 23 22 21 20 DATA 15 14 13 12 DATA 7 6 5 4 DATA This register is used to acces internal FIFO. Even when the data is less than 8 bytes, always read and write 8 bytes of data.
AT32UC3A3 32.7.3 Name : Status register SR Access Type : Read Only Offset : 0x08 Reset Value : 0x00001020 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - ISTA 15 14 13 12 11 10 9 8 - - - RDY - - - - 7 6 5 4 3 2 1 0 - - EMP FUL CED ERR BRQ CNK • ISTA : Insertion Status. It reflects the Memory Stick card presence. This is the inverse of INS pin. 0 : No card. 1 : Card is inserted. • RDY : Ready.
AT32UC3A3 • BRQ : MS Data Buffer Request. In parallel mode, this bit reflects the BREQ bit in the status register of a Memory Stick (INT). It indicates that a host has requested to access a Memory Sticks page buffer.In serial mode, this bit is always 0. It is cleared to 0 by writing to the command register (CMD). • CNK : MS Command No Acknowledge. In parallel mode, this bit reflects the CMDNK bit in the status register of a Memory Stick (INT). It indicates that the command cannot be executed.
AT32UC3A3 32.7.4 Name : System register SYS Access Type : Read/Write Offset : 0x0C Reset Value : 0x00004015 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 CLKDIV 15 14 13 12 11 10 9 8 RST SRAC - NOCRC - - FCLR FDIR 7 6 5 4 3 2 1 0 - - - REI REO BSY • CLKDIV : Clock Division. Write this field to change SCLK frequency = CLK_MSI / (2*(CLKDIV+1)). • RST : Reset. When RST is written, internal synchronous reset is performed.
AT32UC3A3 1 : Write 1 to sample data at the rising edge of SCLK. • REO : Rising Edge output. This bit is used when not fixed hold time by the side of the Memory Stick in parallel communication. This setting cannot be changed during protocol execution. 0 : Write 0 to synchronize outputs with the falling edge of SCLK. 1 : Write 1 to synchronize outputs with the rising edge of SCLK. • BSY : Busy Count. This is the maximum BSY wait time until the RDY signal is output from the Memory Stick.
AT32UC3A3 32.7.5 Name : Interrupt Status register ISR Access Type : Read Only Offset : 0x10 Reset Value : 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - CD TOE CRC MSINT DRQ PEND • CD : Card Detection. 0 : No card detected. This bit is cleared when the correponding bit in ISCR is set to 1.
AT32UC3A3 32.7.6 Name : Interrupt Status Clear register ISCR Access Type : Write Only Offset : 0x14 Reset Value : 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - CD TOE CRC MSINT - PEND • CD : Card Detection clear bit. 0 : Writing 0 has no effect. 1 : Writing 1 clears corresponding bit in ISR. • TOE : Time Out Error clear bit.
AT32UC3A3 32.7.7 Name : Interrupt Enable register IER Access Type : Write Only Offset : 0x18 Reset Value : 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - CD TOE CRC MSINT DRQ PEND • CD : Card Detection interrupt enable. 0 : Writing 0 has no effect. 1 : Writing 1 set to 1 corresponding bit in IMR.
AT32UC3A3 32.7.8 Name : Interrupt Disable register IDR Access Type : Write Only Offset : 0x1C Reset Value : 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - CD TOE CRC MSINT DRQ PEND • CD : Card Detection interrupt disable. 0 : Writing 0 has no effect. 1 : Writing 1 clears to 0 corresponding bit in IMR.
AT32UC3A3 32.7.9 Name : Interrupt Mask register IMR Access Type : Read Only Offset : 0x20 Reset Value : 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - CD TOE CRC MSINT DRQ PEND • CD : Card Detection interrupt mask. 0 : Interrupt is disabled. 1 : Interrupt is enabled. • TOE : Time Out Error interrupt mask. 0 : Interrupt is disabled.
AT32UC3A3 32.7.10 Name : Version Register VERSION Access Type : Read Only Offset : 0x24 Reset Value : 0x00000210 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 1 0 VARIANT 11 10 VERSION[11:8] 3 2 VERSION[7:0] • VARIANT: Variant Number Reserved. No functionality associated. • VERSION : Version Number Version number of the module. No functionality associated.
AT32UC3A3 33. Advanced Encryption Standard (AES) Rev: 1.2.3.1 33.1 Features • Compliant with FIPS Publication 197, Advanced Encryption Standard (AES) • 128-bit/192-bit/256-bit cryptographic key • 12/14/16 clock cycles encryption/decryption processing time with a 128-bit/192-bit/256-bit cryptographic key • Support of the five standard modes of operation specified in the NIST Special Publication 800- • • • • 33.
AT32UC3A3 33.3.2 Clocks The clock for the AES bus interface (CLK_AES) is generated by the Power Manager. This clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the AES before disabling the clock, to avoid freezing the AES in an undefined state. 33.3.3 Interrupts The AES interrupt request line is connected to the interrupt controller. Using the AES interrupt requires the interrupt controller to be programmed first. 33.
AT32UC3A3 These sizes are selected by writing the Cipher Feedback Data Size field in the MR register (MR.CFDS). 33.4.2 Start Modes The Start Mode field in the MR register (MR.SMOD) allows selection of the encryption (or decryption) start mode. 33.4.2.1 Manual mode The sequence is as follows: • Write the 128-bit/192-bit/256-bit key in the KEYWnR registers. • Write the initialization vector (or counter) in the IVnR registers. Note: The Initialization Vector Registers concern all modes except ECB.
AT32UC3A3 33.4.2.3 DMA mode The DMA Controller can be used in association with the AES to perform an encryption/decryption of a buffer without any action by the software during processing. In this starting mode, the type of the data transfer (byte, halfword or word) depends on the operation mode. Table 33-2.
AT32UC3A3 33.4.3.1 Manual and automatic modes • When MR.LOD is zero The ISR.DATRDY bit is cleared when at least one of the ODATAnR registers is read. Figure 33-1. Manual and Automatic Modes when MR.LOD is zero Write CR.START (Manual mode) Or Write IDATAnR register(s) (Auto mode) Read ODATAnR register(s) ISR.DATRDY Encryption or Decryption Process If the user does not want to read the output data registers between each encryption/decryption, the ISR.DATRDY bit will not be cleared. If the ISR.
AT32UC3A3 Figure 33-3. DMA Mode when MR.LOD is zero E n a b le D M A C o n tro lle r C h a n n e ls (R e c e iv e a n d T ra n s m it C h a n n e ls) M u ltip le e n c ry p tio n o r d e c ry p tio n p ro c e s s e s D M A C o n tro lle r In te rru p t • when MR.LOD is one The user must first wait for the DMA Controller Interrupt, then for ISR.DATRDY to ensure that the encryption/decryption is completed. In this case, no receive buffers are required. The output data is only available in ODATAnR registers.
AT32UC3A3 33.4.4 33.4.4.1 Security Features Countermeasures The AES also features hardware countermeasures that can be useful to protect data against Differential Power Analysis (DPA) attacks. These countermeasures can be enabled through the Countermeasure Type field in the MR register (MR.CTYPE). This field is write-only, and all changes to it are taken into account if, at the same time, the Countermeasure Key field in the Mode Register (MR.
AT32UC3A3 33.5 User Interface Table 33-4.
AT32UC3A3 33.5.
AT32UC3A3 33.5.
AT32UC3A3 • CKEY: Countermeasure Key Writing the value 0xE to this field allows the CTYPE field to be modified. Writing another value to this field has no effect. This bit always reads as zero. • CFBS: Cipher Feedback Data Size CFBS Description 0 128-bit 1 64-bit 2 32-bit 3 16-bit 4 8-bit Others Reserved • LOD: Last Output Data Mode Writing a one to this bit will enabled the LOD mode. Writing a zero to this bit will disabled the LOD mode. These mode is described in the Table 33-3 on page 895.
AT32UC3A3 • SMOD: Start Mode SMOD Description 0 Manual mode 1 Automatic mode DMA mode 2 • LOD = 0: The encrypted/decrypted data are available at the address specified in the configuration of DMA Controller. • LOD = 1: The encrypted/decrypted data are available in the ODATAnR registers.
AT32UC3A3 33.5.3 Name: Interrupt Enable Register IER Access Type: Write-only Offset: 0x10 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - URAD 7 6 5 4 3 2 1 0 - - - - - - - DATRDY Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR.
AT32UC3A3 33.5.4 Name: Interrupt Disable Register IDR Access Type: Write-only Offset: 0x14 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - URAD 7 6 5 4 3 2 1 0 - - - - - - - DATRDY Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR.
AT32UC3A3 33.5.5 Name: Interrupt Mask Register IMR Access Type: Read-only Offset: 0x18 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - URAD 7 6 5 4 3 2 1 0 - - - - - - - DATRDY 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled.
AT32UC3A3 33.5.6 Name: Interrupt Status Register ISR Access Type: Read-only Offset: 0x1C Reset Value: 0x0000001E 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - URAD URAT 7 6 5 4 3 2 1 0 - - - - - - - DATRDY • URAT: Unspecified Register Access Type: URAT Description 0 The IDATAnR register during the data processing in DMA mode.
AT32UC3A3 • DATRDY: Data Ready This bit is set/clear as described in the Table 33-3 on page 895. This bit is also cleared when SWRST bit in the Control Register is set to one.
AT32UC3A3 33.5.7 Name: Key Word n Register KEYWnR Access Type: Write-only Offset: 0x20 +(n-1)*0x04 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 18 17 16 11 10 9 8 3 2 1 0 KEYWn[31:24] 23 22 21 20 19 KEYWn[23:16] 15 14 13 12 KEYWn[15:8] 7 6 5 4 KEYWn[7:0] • KEYWn[31:0]: Key Word n Writing the 128-bit/192-bit/256-bit cryptographic key used for encryption/decryption in the four/six/eight 32-bit Key Word registers.
AT32UC3A3 33.5.8 Name: Input Data n Register IDATAnR Access Type: Write-only Offset: 0x40 + (n-1)*0x04 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 18 17 16 11 10 9 8 3 2 1 0 IDATAn[31:24] 23 22 21 20 19 IDATAn[23:16] 15 14 13 12 IDATAn[15:8] 7 6 5 4 IDATAn[7:0] • IDATAn[31:0]: Input Data Word n Writing the 128-bit data block used for encryption/decryption in the four 32-bit Input Data registers.
AT32UC3A3 33.5.9 Name: Output Data n Register ODATAnR Access Type: Read-only Offset: 0x50 + (n-1)*0x04 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 18 17 16 11 10 9 8 3 2 1 0 ODATAn[31:24] 23 22 21 20 19 ODATAn[23:16] 15 14 13 12 ODATAn[15:8] 7 6 5 4 ODATAn[7:0] • ODATAn[31:0]: Output Data n Reading the four 32-bit ODATAnR give the 128-bit data block that has been encrypted/decrypted. ODATA1 corresponds to the first word, ODATA4 to the last one.
AT32UC3A3 33.5.
AT32UC3A3 33.5.11 Name: Version Register VERSION Access Type: Read-only Offset: 0xFC Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant Number Reserved. No functionality associated. • VERSION[11:0] Version number of the module. No functionality associated.
AT32UC3A3 33.6 Module Configuration The specific configuration for each AES instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks according to the table in the System Bus Clock Connections section. Table 33-5. Module clock name Module name Clock name AES CLK_AES Table 33-6.
AT32UC3A3 34. Audio Bitstream DAC (ABDAC) Rev: 1.0.1.1 34.1 Features • Digital Stereo DAC • Oversampled D/A conversion architecture – Oversampling ratio fixed 128x – FIR equalization filter – Digital interpolation filter: Comb4 – 3rd Order Sigma-Delta D/A converters • Digital bitstream outputs • Parallel interface • Connected to DMA Controller for background transfer without CPU intervention 34.
AT32UC3A3 34.3 Block Diagram Figure 34-1. ABDAC Block Diagram Audio Bitstream DAC PM GCLK_ABDAC Clock Generator bit_clk sample_clk CHANNEL0[15:0] Equalization FIR COMB (INT=128) Sigma-Delta DA-MOD DATA0 Equalization FIR COMB (INT=128) Sigma-Delta DA-MOD DATA1 User Interface CHANNEL1[15:0] 34.4 I/O Lines Description Table 34-1.
AT32UC3A3 34.5.2 Clocks The CLK_ABDAC to the Audio Bitstream DAC is generated by the Power Manager (PM). Before using the Audio Bitstream DAC, the user must ensure that the Audio Bitstream DAC clock is enabled in the Power Manager. The ABDAC needs a separate clock for the D/A conversion operation. This clock, GCLK_ABDAC should be set up in the Generic Clock register in the Power Manager and its frequency must be as follow: f GCLK = 256 × f S where fs is the samping rate of the data stream to convert.
AT32UC3A3 If one want to get coherence between the sign of the input data and the output voltage one can use the DATAN signal or invert the sign of the input data by software. 34.6.3 Data Swapping When the SWAP bit in the ABDAC Control Register (CR.SWAP) is written to one, writing to the Sample Data Register (SDR) will cause the values written to the CHANNEL0 and CHANNEL1 fields to be swapped. 34.6.4 Peripheral DMA Controller The Audio Bitstream DAC is connected to the Peripheral DMA Controller.
AT32UC3A3 34.6.9 Frequency Response Figure 34-2.
AT32UC3A3 34.7 User Interface Table 34-2.
AT32UC3A3 34.7.1 Name: Sample Data Register SDR Access Type: Read/Write Offset: 0x00 Reset Value: 0x00000000 31 30 29 28 27 CHANNEL1[15:8] 26 25 24 23 22 21 20 19 CHANNEL1[7:0] 18 17 16 15 14 13 12 11 CHANNEL0[15:8] 10 9 8 7 6 5 4 3 CHANNEL0[7:0] 2 1 0 • CHANNEL1: Sample Data for Channel 1 signed 16-bit Sample Data for channel 1. • CHANNEL0: Signed 16-bit Sample Data for Channel 0 signed 16-bit Sample Data for channel 0.
AT32UC3A3 34.7.2 Name: Control Register CR Access Type: Read/Write Offset: 0x08 Reset Value: 0x00000000 31 EN 30 SWAP 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 - • EN: Enable Audio Bitstream DAC 1: The module is enabled. 0: The module is disabled. • SWAP: Swap Channels 1: The swap of CHANNEL0 and CHANNEL1 samples is enabled.
AT32UC3A3 34.7.3 Name: Interrupt Mask Register IMR Access Type: Read-only Offset: 0x0C Reset Value: 0x00000000 31 - 30 - 29 TXREADY 28 UNDERRUN 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 - 1: The corresponding interrupt is enabled. 0: The corresponding interrupt is disabled. A bit in this register is set when the corresponding bit in IER is written to one.
AT32UC3A3 34.7.4 Name: Interrupt Enable Register IER Access Type: Write-only Offset: 0x10 Reset Value: 0x00000000 31 - 30 - 29 TXREADY 28 UNDERRUN 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 - Writing a one to a bit in this register will set the corresponding bit in IMR. Writing a zero to a bit in this register has no effect.
AT32UC3A3 34.7.5 Name: Interrupt Disable Register IDR Access Type: Write-only Offset: 0x14 Reset Value: 0x00000000 31 - 30 - 29 TXREADY 28 UNDERRUN 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 - Writing a one to a bit in this register will clear the corresponding bit in IMR. Writing a zero to a bit in this register has no effect.
AT32UC3A3 34.7.6 Name: Interrupt Clear Register ICR Access Type: Write-only Offset: 0x18 Reset Value: 0x00000000 31 - 30 - 29 TXREADY 28 UNDERRUN 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 - Writing a one to a bit in this register will clear the corresponding bit in ISR and the corresponding interrupt request. Writing a zero to a bit in this register has no effect.
AT32UC3A3 34.7.7 Name: Interrupt Status Register ISR Access Type: Read-only Offset: 0x1C Reset Value: 0x00000000 31 - 30 - 29 TXREADY 28 UNDERRUN 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 - • TXREADY: TX Ready Interrupt Status This bit is set when the Audio Bitstream DAC is ready to receive a new data in SDR.
AT32UC3A3 35. Programming and Debugging 35.1 Overview General description of programming and debug features, block diagram and introduction of main concepts. 35.2 Service Access Bus The AVR32 architecture offers a common interface for access to On-Chip Debug, programming, and test functions. These are mapped on a common bus called the Service Access Bus (SAB), which is linked to the JTAG port through a bus master module, which also handles synchronization between the debugger and SAB clocks.
AT32UC3A3 35.2.2.1 Security measure and control location A security measure is a mechanism to either block or allow SAB access to a certain address or address range. A security measure is enabled or disabled by one or several control signals. This is called the control location for the security measure. These security measures can be used to prevent an end user from reading out the code programmed in the flash, for instance. Table 35-2. SAB Security measures.
AT32UC3A3 35.3 On-Chip Debug (OCD) Rev: 1.4.2.1 35.3.1 Features • • • • • • • • 35.3.2 Debug interface in compliance with IEEE-ISTO 5001-2003 (Nexus 2.
AT32UC3A3 35.3.3 Block Diagram Figure 35-1. On-Chip Debug Block Diagram JTAG JTAG AUX On-Chip Debug Memory Service Unit Service Access Bus Transmit Queue Watchpoints Debug PC Debug Instruction Breakpoints CPU 35.3.4 Program Trace Internal SRAM HSB Bus Matrix Data Trace Ownership Trace Memories and peripherals JTAG-based Debug Features A debugger can control all OCD features by writing OCD registers over the JTAG interface.
AT32UC3A3 Figure 35-2. JTAG-based Debugger PC JTAG-based debug tool 10-pin IDC JTAG AVR32 35.3.4.1 Debug Communication Channel The Debug Communication Channel (DCC) consists of a pair OCD registers with associated handshake logic, accessible to both CPU and JTAG. The registers can be used to exchange data between the CPU and the JTAG master, both runtime as well as in debug mode. 35.3.4.
AT32UC3A3 35.3.4.3 OCD mode When a breakpoint triggers, the CPU enters OCD mode, and instructions are fetched from the Debug Instruction OCD register. Each time this register is written by JTAG, the instruction is executed, allowing the JTAG to execute CPU instructions directly. The JTAG master can e.g. read out the register file by issuing mtdr instructions to the CPU, writing each register to the Debug Communication Channel OCD registers. 35.3.4.
AT32UC3A3 Debug tools utilizing the AUX port should connect to the device through a Nexus-compliant Mictor-38 connector, as described in the AVR32UC Technical Reference manual. This connector includes the JTAG signals and the RESET_N pin, giving full access to the programming and debug features in the device. Table 35-5.
AT32UC3A3 The trace features can be configured to be very selective, to reduce the bandwidth on the AUX port. In case the transmit queue overflows, error messages are produced to indicate loss of data. The transmit queue module can optionally be configured to halt the CPU when an overflow occurs, to prevent the loss of messages, at the expense of longer run-time for the program. 35.3.6.2 program trace Program trace allows the debugger to continuously monitor the program execution in the CPU.
AT32UC3A3 35.3.6.7 Software Quality Analysis (SQA) Software Quality Analysis (SQA) deals with two important issues regarding embedded software development. Code coverage involves identifying untested parts of the embedded code, to improve test procedures and thus the quality of the released software. Performance analysis allows the developer to precisely quantify the time spent in various parts of the code, allowing bottlenecks to be identified and optimized.
AT32UC3A3 35.4 JTAG and Boundary-scan (JTAG) Rev: 2.0.0.4 35.4.1 Features • IEEE1149.1 compliant JTAG Interface • Boundary-scan Chain for board-level testing • Direct memory access and programming capabilities through JTAG Interface 35.4.2 Overview The JTAG Interface offers a four pin programming and debug solution, including boundary-scan support for board-level testing. Figure 35-4 on page 936 shows how the JTAG is connected in an 32-bit AVR device.
AT32UC3A3 35.4.3 Block Diagram Figure 35-4. JTAG and Boundary-scan Access 32-bit AVR device JTAG JTAG master Boundary scan enable TAP Controller TDO TDI JTAG Pins TMS TCK TCK TMS TDI TDO Instruction register scan enable Data register scan enable Instruction Register TMS TCK TDO TDI JTAG data registers 2nd JTAG device Device Identification Register Reset Register Part specific registers ...
AT32UC3A3 35.4.5.1 Power Management When an instruction that accesses the SAB is loaded in the instruction register, before entering a sleep mode, the system clocks are not switched off to allow debugging in sleep modes. This can lead to a program behaving differently when debugging. 35.4.5.2 Clocks The JTAG Interface uses the external TCK pin as clock source. This clock must be provided by the JTAG master. Instructions that use the SAB bus requires the internal main clock to be running. 35.4.
AT32UC3A3 Figure 35-5.
AT32UC3A3 35.4.7 How to Initialize the Module Independent of the initial state of the TAP Controller, the Test-Logic-Reset state can always be entered by holding TMS high for 5 TCK clock periods. This sequence should always be applied at the start of a JTAG session to bring the TAP Controller into a defined state before applying JTAG commands. Applying a 0 on TMS for 1 TCK period brings the TAP Controller to the RunTest/Idle state, which is the starting point for JTAG operations. 35.4.8 35.4.8.
AT32UC3A3 Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. If the selected Data Register has a latched parallel-output, the latching takes place in the Update-DR state. The Exit-DR, Pause-DR, and Exit2-DR states are only used for navigating the state machine. As shown in the state diagram, the Run-Test/Idle state need not be entered between selecting JTAG instruction and using Data Registers. 35.4.
AT32UC3A3 For more information about the SAB and a list of SAB slaves see the Service Access Bus chapter. 35.4.10.1 SAB Address Mode The MEMORY_SIZED_ACCESS instruction allows a sized read or write to any 36-bit address on the bus. MEMORY_WORD_ACCESS is a shorthand instruction for 32-bit accesses to any 36-bit address, while the NEXUS_ACCESS instruction is a Nexus-compliant shorthand instruction for accessing the 32-bit OCD registers in the 7-bit address space reserved for these.
AT32UC3A3 • During Shift-DR of read data: The read data is invalid. The SAB stays in data mode. Repeat scanning until the busy bit clears. • During Shift-DR of write data: The write data is ignored. The SAB stays in data mode. Repeat scanning until the busy bit clears. 35.4.10.5 Error Reporting The Service Access Bus may not be able to complete all accesses as requested.
AT32UC3A3 35.5 JTAG Instruction Summary The implemented JTAG instructions in the 32-bit AVR are shown in the table below. Table 35-7. Instruction OPCODE JTAG Instruction Summary Instruction Description 0x01 IDCODE Select the 32-bit Device Identification register as data register. 0x02 SAMPLE_PRELOAD Take a snapshot of external pin values without affecting system operation. 0x03 EXTEST Select boundary-scan chain as data register for testing circuitry external to the device.
AT32UC3A3 Other security mechanisms can also restrict these functions. If such mechanisms are present they are listed in the SAB address map section. 35.5.1.1 Notation Table 35-9 on page 944 shows bit patterns to be shifted in a format like "peb01". Each character corresponds to one bit, and eight bits are grouped together for readability. The least significantbit is always shifted first, and the most significant bit shifted last. The symbols used are shown in Table 35-8. Table 35-8.
AT32UC3A3 Table 35-9. 35.5.2 35.5.2.1 Instruction Description (Continued) Instruction Description DR Size Shows the number of bits in the data register chain when this instruction is active. Example: 34 bits DR input value Shows which bit pattern to shift into the data register in the Shift-DR state when this instruction is active. Multiple such lines may exist, e.g., to distinguish between reads and writes.
AT32UC3A3 1. Select the IR Scan path. 2. In Capture-IR: The IR output value is latched into the shift register. 3. In Shift-IR: The instruction register is shifted by the TCK input. 4. Return to Run-Test/Idle. 5. Select the DR Scan path. 6. In Capture-DR: The Data on the external pins are sampled into the boundary-scan chain. 7. In Shift-DR: The boundary-scan chain is shifted by the TCK input. 8. Return to Run-Test/Idle. Table 35-11. SAMPLE_PRELOAD Details 35.5.2.
AT32UC3A3 35.5.2.4 INTEST This instruction selects the boundary-scan chain as Data Register for testing internal logic in the device. The logic inputs are determined by the boundary-scan chain, and the logic outputs are captured by the boundary-scan chain. The device output pins are driven from the boundary-scan chain. Starting in Run-Test/Idle, the INTEST instruction is accessed the following way: 1. Select the IR Scan path. 2. In Capture-IR: The IR output value is latched into the shift register. 3.
AT32UC3A3 9. Return to Run-Test/Idle. Table 35-14. CLAMP Details 35.5.2.6 Instructions Details IR input value 00110 (0x06) IR output value p0001 DR Size 1 DR input value x DR output value x BYPASS This instruction selects the 1-bit Bypass Register as Data Register. Starting in Run-Test/Idle, the CLAMP instruction is accessed the following way: 1. Select the IR Scan path. 2. In Capture-IR: The IR output value is latched into the shift register. 3.
AT32UC3A3 Starting in Run-Test/Idle, OCD registers are accessed in the following way: 1. Select the IR Scan path. 2. In Capture-IR: The IR output value is latched into the shift register. 3. In Shift-IR: The instruction register is shifted by the TCK input. 4. Return to Run-Test/Idle. 5. Select the DR Scan path. 6. In Shift-DR: Scan in the direction bit (1=read, 0=write) and the 7-bit address for the OCD register. 7. Go to Update-DR and re-enter Select-DR Scan. 8.
AT32UC3A3 7. Go to Update-DR and re-enter Select-DR Scan. 8. In Shift-DR: For a read operation, scan out the contents of the addressed register. For a write operation, scan in the new contents of the register. 9. Return to Run-Test/Idle. For any operation, the full 7 bits of the address must be provided. For write operations, 32 data bits must be provided, or the result will be undefined. For read operations, shifting may be terminated once the required number of bits have been acquired. Table 35-17.
AT32UC3A3 The size field is encoded as i Table 35-18. Table 35-18.
AT32UC3A3 Table 35-19. MEMORY_SIZED_ACCESS Details (Continued) 35.5.3.4 Instructions Details DR output value (Address phase) xxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxeb DR output value (Data read phase) xxxxxeb dddddddd dddddddd dddddddd dddddddd DR output value (Data write phase) xxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxeb MEMORY_WORD_ACCESS This instruction allows access to the entire Service Access Bus data area.
AT32UC3A3 Table 35-20. MEMORY_WORD_ACCESS Details (Continued) 35.5.3.5 Instructions Details DR output value (Address phase) xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xeb DR output value (Data read phase) xeb dddddddd dddddddd dddddddd dddddddd DR output value (Data write phase) xxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxeb MEMORY_BLOCK_ACCESS This instruction allows access to the entire SAB data area.
AT32UC3A3 Table 35-21. MEMORY_BLOCK_ACCESS Details (Continued) Instructions Details DR input value (Data write phase) dddddddd dddddddd dddddddd dddddddd xx DR output value (Data read phase) eb dddddddd dddddddd dddddddd dddddddd DR output value (Data write phase) xx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxeb The overhead using block word access is 4 cycles per 32 bits of data, resulting in an 88% transfer efficiency, or 2.1 MBytes per second with a 20 MHz TCK frequency. 35.5.3.
AT32UC3A3 6. Scan in an 16-bit counter value. 7. Go to Update-DR and re-enter Select-DR Scan. 8. In Shift-DR: Scan out the busy bit, and until the busy bit clears goto 7. 9. Calculate an approximation to the internal clock speed using the elapsed time and the counter value. 10. Return to Run-Test/Idle. The full 16-bit counter value must be provided when starting the synch operation, or the result will be undefined.
AT32UC3A3 Table 35-24. AVR_RESET Details (Continued) 35.5.3.9 Instructions Details DR Size Device specific. DR input value Device specific. DR output value Device specific. CHIP_ERASE This instruction allows a programmer to completely erase all nonvolatile memories in a chip. This will also clear any security bits that are set, so the device can be accessed normally. In devices without non-volatile memories this instruction does nothing, and appears to complete immediately.
AT32UC3A3 6. In Shift-DR: Scan in the value 1 to halt the CPU, 0 to start CPU execution. 7. Return to Run-Test/Idle. Table 35-26.
AT32UC3A3 35.5.4 35.5.4.1 JTAG Data Registers The following device specific registers can be selected as JTAG scan chain depending on the instruction loaded in the JTAG Instruction Register. Additional registers exist, but are implicitly described in the functional description of the relevant instructions. Device Identification Register The Device Identification Register contains a unique identifier for each product.
AT32UC3A3 35.5.4.2 Reset register The reset register is selected by the AVR_RESET instruction and contains one bit for each reset domain in the device. Setting each bit to one will keep that domain reset until the bit is cleared. LSB Bit Device ID 4 3 2 1 0 OCD APP RESERVED RESERVED CPU CPU CPU APP HSB and PB buses OCD On-Chip Debug logic and registers RSERVED No effect Note: This register is primarily intended for compatibility with other 32-bit AVR devices.
AT32UC3A3 36. Electrical Characteristics 36.1 Absolute Maximum Ratings* Operating Temperature.................................... -40°C to +85°C Storage Temperature ..................................... -60°C to +150°C Voltage on Input Pin with respect to Ground ........................................-0.3V to 3.6V Maximum Operating Voltage (VDDCORE) ..................... 1.95V *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
AT32UC3A3 36.2 DC Characteristics The following characteristics are applicable to the operating temperature range: T A = -40°C to 85°C, unless otherwise specified and are certified for a junction temperature up toTJ = 100°C. Table 36-1. DC Characteristics Symbol Parameter VVDDIO DC Supply Peripheral I/Os VVDDANA DC Analog Supply Conditions Min. Max. Unit 3.0 3.6 V 3.0 3.6 V -0.3 +0.8 V TWCK, TWD VVDDIO x0.7 VVDDIO +0.5 V RESET_N, TCK, TDI +0.
AT32UC3A3 36.2.1 I/O Pin Output Level Typical Characteristics Figure 36-1. I/O Pin drive x2 Output Low Level Voltage (VOL) vs. Source Current VddIo = 3.3V 1,8 90 1,6 25 1,4 -45 Voltage [V 1,2 1 0,8 0,6 0,4 0,2 0 0 5 10 15 20 Load current [mA] Figure 36-2. I/O Pin drive x2 Output High Level Voltage (VOH) vs. Source Current VddIo = 3.3V 3,5 3 Voltage [V 2,5 -45 25 90 2 1,5 1 0,5 0 0 5 10 15 20 Load current [mA] 36.
AT32UC3A3 Table 36-2. Symbol fMAX Parameter Output frequency Rise time tRISE Fall time tFALL 36.4 Normal I/O Pin Characteristics Conditions drive x2 drive x2 drive x3 Unit 10pf 40 66 100 MHz 30pf 18.2 35.7 61.6 MHz 60pf 7.5 18.5 36.3 MHz 10pf 2.7 1.4 0.9 ns 30pf 6.9 3.5 1.9 ns 60pf 13.4 6.7 3.5 ns 10pf 3.2 1.7 0.9 ns 30pf 8.6 4.3 2.26 ns 60pf 16.5 8.3 4.3 ns Regulator characteristics Table 36-3.
AT32UC3A3 36.5 Analog characteristics 36.5.1 ADC Table 36-5. Electrical Characteristics Symbol Parameter VVDDANA Analog Power Supply Table 36-6. Conditions Typ. Max. Unit 3.0 3.6 V Typ. Technology Unit 100 NPO nF Decoupling Requirements Symbol Parameter CVDDANA Power Supply Capacitor 36.5.2 Min. Conditions BOD Table 36-7. Symbol 1.8V BOD Level Values Parameter Value Conditions Min. Typ. Max. Unit 00 1111b 1.79 V 01 0111b 1.70 V 01 1111b 1.61 V 10 0111b 1.
AT32UC3A3 Table 36-9. BOD Timing Symbol Parameter Conditions TBOD Minimum time with VDDCORE < VBOD to detect power failure Falling VDDCORE from 1.8V to 1.1V 36.5.3 Min. Typ. Max. Unit 300 800 ns Typ. Max. Unit Reset Sequence Table 36-10. Electrical Characteristics Symbol Parameter Conditions Min.
AT32UC3A3 Figure 36-3. MCU Cold Start-Up VDDIN VDDIO VBOD33LEVEL VBOD33LEVEL VRESTART RESET_N Internal BOD33 Reset TSSU1 Internal MCU Reset Figure 36-4. MCU Cold Start-Up RESET_N Externally Driven VDDIN VDDIO VBOD33LEVEL VBOD33LEVEL VRESTART RESET_N Internal BOD33 Reset TSSU1 Internal MCU Reset Figure 36-5.
AT32UC3A3 36.5.4 RESET_N Characteristics Table 36-11. RESET_N Waveform Parameters Symbol Parameter tRESET RESET_N minimum pulse width Conditions Min. 10 Typ. Max.
AT32UC3A3 36.6 Power Consumption The values in Table 36-12 and Table 36-13 on page 970 are measured values of power consumption with operating conditions as follows: •VDDIO = 3.3V •TA = 25°C •I/Os are configured in input, pull-up enabled. Figure 36-6.
AT32UC3A3 Power Consumtion for Different Sleep Modes 36.6.1 Table 36-12. Power Consumption for Different Sleep Modes Conditions(1) Mode Typ. Unit - CPU running a recursive Fibonacci Algorithm from flash and clocked from PLL0 at f MHz. - Flash High Speed mode disable (f < 66 MHz) - Voltage regulator is on. - XIN0: external clock. Xin1 Stopped. XIN32 stopped. - All peripheral clocks activated with a division by 8.
AT32UC3A3 Table 36-13. Typical Cuurent Consumption by Peripheral Peripheral Typ. ADC 7 AES 80 ABDAC 10 DMACA 70 EBI 23 EIC 0.
AT32UC3A3 36.7 System Clock Characteristics These parameters are given in the following conditions: • VDDCORE = 1.8V 36.7.1 CPU/HSB Clock Characteristics Table 36-14. Core Clock Waveform Parameters Symbol Parameter Conditions 1/(tCPCPU) CPU Clock Frequency 1/(tCPCPU) CPU Clock Frequency 36.7.2 Min. Typ. Max. Unit -40°C < Ambient Temperature < 70°C 84 MHz -40°C < Ambient Temperature < 85°C 66 MHz Max. Unit PBA Clock Characteristics Table 36-15.
AT32UC3A3 36.8 Oscillator Characteristics The following characteristics are applicable to the operating temperature range: TA = -40°C to 85°C and worst case of power supply, unless otherwise specified. 36.8.1 Slow Clock RC Oscillator Table 36-17. RC Oscillator Frequency Symbol Parameter Conditions Min. Calibration point: TA = 85°C FRC RC Oscillator Frequency 36.8.2 TA = 25°C Typ. Max. Unit 115.2 116 KHz 112 KHz KHz TA = -40°C 105 108 Conditions Min. Typ.
AT32UC3A3 36.8.3 Main Oscillators Table 36-19. Main Oscillators Characteristics Symbol Parameter 1/(tCPMAIN) Oscillator Frequency CL1, CL2 Internal Load Capacitance (CL1 = CL2) ESR Crystal Equivalent Series Resistance Conditions Min. Typ. External clock on XIN Crystal 0.4 Max. Unit 50 MHz 20 MHz 7 Duty Cycle 40 f = 400 KHz f = 8 MHz f = 16 MHz f = 20 MHz 50 pF 75 Ω 60 % 25 4 1.4 1 tST Startup Time tCH XIN Clock High Half-period 0.4 tCP 0.
AT32UC3A3 36.9 ADC Characteristics Table 36-22. Channel Conversion Time and ADC Clock Parameter Conditions ADC Clock Frequency Startup Time Max. Unit 10-bit resolution mode 5 MHz 8-bit resolution mode 8 MHz Return from Idle Mode 20 µs Track and Hold Acquisition Time Min. Typ. 600 ns ADC Clock = 5 MHz Conversion Time Throughput Rate 2 µs ADC Clock = 8 MHz 1.25 µs ADC Clock = 5 MHz 384 (1) kSPS ADC Clock = 8 MHz 533 (2) kSPS 1.
AT32UC3A3 Table 36-26. Transfer Characteristics in 10-bit mode Parameter Conditions Min. Typ. Resolution Max. Unit 3 LSB 10 Bit Absolute Accuracy ADC Clock = 5 MHz Integral Non-linearity ADC Clock = 5 MHz 1.5 2 LSB ADC Clock = 5 MHz 1 2 LSB 0.6 1 LSB Differential Non-linearity ADC Clock = 2.5 MHz Offset Error ADC Clock = 5 MHz -2 2 LSB Gain Error ADC Clock = 5 MHz -2 2 LSB Max. Unit 36.10 USB Transceiver Characteristics 36.10.1 Electrical Characteristics Table 36-27.
AT32UC3A3 Table 36-29. Dynamic Power Consumption Symbol IVDDUTMI 1. 34.5.5 Parameter Conditions HS Transceiver current consumption Min. Typ. Max. Unit HS transmission 47 60 mA HS Transceiver current consumption HS reception 18 27 mA FS/HS Transceiver current consumption FS transmission 0m cable (1) 4 6 mA FS/HS Transceiver current consumption FS transmission 5m cable 26 30 mA FS/HS Transceiver current consumption FS reception 3 4.
AT32UC3A3 36.11 EBI Timings 36.11.1 SMC Signals These timings are given for worst case process, T = 85⋅C, VDDIO = 3V and 40 pF load capacitance. Table 36-30. SMC Clock Signal Symbol Parameter Max.(1) Unit 1/(tCPSMC) SMC Controller Clock Frequency 1/(tcpcpu) MHz Note: 1. The maximum frequency of the SMC interface is the same as the max frequency for the HSB. Table 36-31. SMC Read Signals with Hold Settings Symbol Parameter Min.
AT32UC3A3 Table 36-32. SMC Read Signals with no Hold Settings Symbol Parameter Min. Unit 13.7 ns 1 ns 13.3 ns 0 ns Min. Unit NRD Controlled (READ_MODE = 1) SMC19 Data Setup before NRD High SMC20 Data Hold after NRD High NRD Controlled (READ_MODE = 0) SMC21 Data Setup before NCS High SMC22 Data Hold after NCS High Table 36-33.
AT32UC3A3 Table 36-34. SMC Write Signals with No Hold Settings (NWE Controlled only) Symbol Parameter SMC43 Data Out Valid before NWE Rising SMC44 Data Out Valid after NWE Rising SMC45 NWE Pulse Width Min. Unit (nwe pulse length - 1) * tCPSMC - 1.2 ns 5 ns nwe pulse length * tCPSMC - 0.9 ns Figure 36-7. SMC Signals for NCS Controlled Accesses.
AT32UC3A3 Figure 36-8. SMC Signals for NRD and NRW Controlled Accesses. SMC37 SMC7 SMC7 SMC31 A2-A25 SMC25 SMC26 SMC29 SMC30 SMC3 SMC4 SMC5 SMC6 SMC38 SMC39 SMC40 SMC41 SMC3 SMC4 SMC5 SMC6 A0/A1/NBS[3:0] SMC42 SMC32 SMC8 NCS SMC8 SMC9 SMC9 NRD SMC19 SMC20 SMC43 SMC44 SMC1 SMC23 SMC2 SMC24 D0 - D15 SMC33 SMC45 NWE 36.11.2 SDRAM Signals These timings are given for 10 pF load on SDCK and 40 pF on other signals. Table 36-35. SDRAM Clock Signal.
AT32UC3A3 Table 36-36. SDRAM Clock Signal Symbol Parameter Conditions Min. Max. Unit SDRAMC13 Bank Change before SDCK Rising Edge 6.3 ns SDRAMC14 Bank Change after SDCK Rising Edge 2.4 ns SDRAMC15 CAS Low before SDCK Rising Edge 7.4 ns SDRAMC16 CAS High after SDCK Rising Edge 1.9 ns SDRAMC17 DQM Change before SDCK Rising Edge 6.4 ns SDRAMC18 DQM Change after SDCK Rising Edge 2.
AT32UC3A3 Figure 36-9. SDRAMC Signals relative to SDCK.
AT32UC3A3 36.12 JTAG Characteristics 36.12.1 JTAG Interface Signals Table 36-37. JTAG Interface Timing Specification Conditions (1) Symbol Parameter Min. Max.
AT32UC3A3 Figure 36-10. JTAG Interface Signals JTAG2 TCK JTAG JTAG1 0 TMS/TDI JTAG3 JTAG4 JTAG7 JTAG8 TDO JTAG5 JTAG6 Device Inputs Device Outputs JTAG9 JTAG10 36.13 SPI Characteristics Figure 36-11.
AT32UC3A3 Figure 36-12. SPI Master mode with (CPOL= 0 and NCPHA= 1) or (CPOL= 1 and NCPHA= 0) SPCK SPI3 SPI4 MISO SPI5 MOSI Figure 36-13. SPI Slave mode with (CPOL= 0 and NCPHA= 1) or (CPOL= 1 and NCPHA= 0) SPCK SPI6 MISO SPI7 SPI8 MOSI Figure 36-14.
AT32UC3A3 Table 36-38. SPI Timings Symbol Parameter Conditions (1) SPI0 MISO Setup time before SPCK rises (master) 3.3V domain 22 + (tCPMCK)/2 (2) ns SPI1 MISO Hold time after SPCK rises (master) 3.3V domain 0 ns SPI2 SPCK rising to MOSI Delay (master) 3.3V domain SPI3 MISO Setup time before SPCK falls (master) 3.3V domain 22 + (tCPMCK)/2 (3) ns SPI4 MISO Hold time after SPCK falls (master) 3.3V domain 0 ns SPI5 SPCK falling to MOSI Delay master) 3.
AT32UC3A3 36.15 Flash Memory Characteristics The following table gives the device maximum operating frequency depending on the field FWS of the Flash FSR register. This field defines the number of wait states required to access the Flash Memory. Flash operating frequency equals the CPU/HSB frequency. Table 36-39. Flash Operating Frequency Symbol FFOP Parameter Conditions Min. Typ. Max.
AT32UC3A3 37. Mechanical Characteristics 37.1 37.1.1 Thermal Considerations Thermal Data Table 37-1 summarizes the thermal resistance data depending on the package. Table 37-1. 37.1.2 Thermal Resistance Data Symbol Parameter Condition Package Typ θJA Junction-to-ambient thermal resistance Still Air TQFP144 40.3 θJC Junction-to-case thermal resistance TQFP144 9.5 θJA Junction-to-ambient thermal resistance TFBGA144 28.5 θJC Junction-to-case thermal resistance TFBGA144 6.
AT32UC3A3 37.2 Package Drawings Figure 37-1.
AT32UC3A3 Figure 37-2. LQFP-144 package drawing Table 37-2. Device and Package Maximum Weight 1300 Table 37-3. mg Package Characteristics Moisture Sensitivity Level Table 37-4.
AT32UC3A3 Figure 37-3.
AT32UC3A3 37.3 Soldering Profile Table 37-5 gives the recommended soldering profile from J-STD-20. Table 37-5. Soldering Profile Profile Feature Green Package Average Ramp-up Rate (217°C to Peak) 3°C/Second max Preheat Temperature 175°C ±25°C 150-200°C Time Maintained Above 217°C 60-150 seconds Time within 5°C of Actual Peak Temperature 30 seconds Peak Temperature Range 260 (+0/-5°C) Ramp-down Rate 6°C/Second max.
AT32UC3A3 38.
AT32UC3A3 39. Errata 39.1 39.1.1 Rev. H General Devices with Date Code lower than 1233 cannot operate with CPU frequency higher than 66MHz in 1WS and 36MHz in 0WS in the whole temperature range Fix/Workaround None DMACA data transfer fails when CTLx.SRC_TR_WIDTH is not equal CTLx.DST_TR_WIDTH Fix/Workaround For any DMACA transfer make sure CTLx.SRC_TR_WIDTH = CTLx.DST_TR_WIDTH. 39.1.
AT32UC3A3 For higher polling time, the software must freeze the pipe for the desired period in order to prevent any "extra" token. 39.1.4 ADC Sleep Mode activation needs additional A to D conversion If the ADC sleep mode is activated when the ADC is idle the ADC will not enter sleep mode before after the next AD conversion. Fix/Workaround Activate the sleep mode in the mode register and then perform an AD conversion. 39.1.
AT32UC3A3 SPI data transfer hangs with CSR0.CSAAT==1 and MR.MODFDIS==0 When CSR0.CSAAT==1 and mode fault detection is enabled (MR.MODFDIS==0), the SPI module will not start a data transfer. Fix/Workaround Disable mode fault detection by writing a one to MR.MODFDIS. Disabling SPI has no effect on the SR.TDRE bit Disabling SPI has no effect on the SR.TDRE bit whereas the write data command is filtered when SPI is disabled. Writing to TDR when SPI is disabled will not clear SR.TDRE.
AT32UC3A3 URAD (Unspecified Register Access Detection Status) does not detect read accesses to the write-only KEYW[5..8]R registers Fix/Workaround None. 39.1.6 HMATRIX In the PRAS and PRBS registers, the MxPR fields are only two bits In the PRAS and PRBS registers, the MxPR fields are only two bits wide, instead of four bits. The unused bits are undefined when reading the registers. Fix/Workaround Mask undefined bits when reading PRAS and PRBS. 39.1.7 TWIM TWIM SR.
AT32UC3A3 Fix/Workaround None. SSC Frame Synchro and Frame Synchro Data are delayed by one clock cycle The frame synchro and the frame synchro data are delayed from 1 SSC_CLOCK when: - Clock is CKDIV - The START is selected on either a frame synchro edge or a level - Frame synchro data is enabled - Transmit clock is gated on output (through CKO field) Fix/Workaround Transmit or receive CLOCK must not be gated (by the mean of CKO field) when START condition is performed on a generated frame synchro. 39.1.
AT32UC3A3 DMACA data transfer fails when CTLx.SRC_TR_WIDTH is not equal CTLx.DST_TR_WIDTH Fix/Workaround For any DMACA transfer make sure CTLx.SRC_TR_WIDTH = CTLx.DST_TR_WIDTH. to 3.3V supply monitor is not available FGPFRLO[30:29] are reserved and should not be used by the application. Fix/Workaround None. Service access bus (SAB) can not access DMACA registers Fix/Workaround None.
AT32UC3A3 39.2.3 ADC Sleep Mode activation needs additional A to D conversion If the ADC sleep mode is activated when the ADC is idle the ADC will not enter sleep mode before after the next AD conversion. Fix/Workaround Activate the sleep mode in the mode register and then perform an AD conversion. 39.2.4 USART ISO7816 info register US_NER cannot be read The NER register always returns zero. Fix/Workaround None.
AT32UC3A3 SPI disable does not work in SLAVE mode SPI disable does not work in SLAVE mode. Fix/Workaround Read the last received data, then perform a software reset by writing a one to the Software Reset bit in the Control Register (CR.SWRST). SPI bad serial clock generation on 2nd chip_select when SCBR=1, CPOL=1, and NCPHA=0 When multiple chip selects (CS) are in use, if one of the baudrates equal 1 while one (CSRn.SCBR=1) of the others do not equal 1, and CSRn.CPOL=1 and CSRn.
AT32UC3A3 PCONTROL.CHxRES is non-functional PCONTROL.CHxRES is non-functional. Counters are reset at power-on, and cannot be reset by software. Fix/Workaround Software needs to keep history of performance counters. Transfer error will stall a transmit peripheral handshake interface If a transfer error is encountered on a channel transmitting to a peripheral, the peripheral handshake of the active channel will stall and the PDCA will not do any more transfers on the affected peripheral handshake interface.
AT32UC3A3 TWIS Clearing the NAK bit before the BTF bit is set locks up the TWI bus When the TWIS is in transmit mode, clearing the NAK Received (NAK) bit of the Status Register (SR) before the end of the Acknowledge/Not Acknowledge cycle will cause the TWIS to attempt to continue transmitting data, thus locking up the bus. Fix/Workaround Clear SR.NAK only after the Byte Transfer Finished (BTF) bit of the same register has been set.
AT32UC3A3 After these commands, read 3 times one flash page initialized to 00h. Disable the flash high speed mode (FLASHC HSDIS command). It is then possible to safely read or code fetch the flash. 39.3 39.3.1 Rev. D General Devices cannot operate with CPU frequency higher than 66MHz in 1WS and 36MHz in 0WS Fix/Workaround None DMACA data transfer fails when CTLx.SRC_TR_WIDTH is not equal CTLx.DST_TR_WIDTH Fix/Workaround For any DMACA transfer make sure CTLx.SRC_TR_WIDTH = CTLx.DST_TR_WIDTH. to 3.
AT32UC3A3 RETS behaves incorrectly when MPU is enabled RETS behaves incorrectly when MPU is enabled and MPU is configured so that system stack is not readable in unprivileged mode. Fix/Workaround Make system stack readable in unprivileged mode, or return from supervisor mode using rete instead of rets. This requires: 1. Changing the mode bits from 001 to 110 before issuing the instruction. Updating the mode bits to the desired value must be done using a single mtsr instruction so it is done atomically.
AT32UC3A3 Fix/Workaround None. The LIN ID is not transmitted in mode PDCM='0' Fix/Workaround Using USART in mode LIN master with the PDCM bit = '0', the LINID written at the first address of the transmit buffer is not used. The LINID must be written in the LINIR register, after the configuration and start of the PDCA transfer. Writing the LINID in the LINIR register will start the transfer whenever the PDCA transfer is ready.
AT32UC3A3 Fix/Workaround When multiple CS are in use, if one of the baudrates equals 1, the others must also equal 1 if CSRn.CPOL=1 and CSRn.NCPHA=0. SPI data transfer hangs with CSR0.CSAAT==1 and MR.MODFDIS==0 When CSR0.CSAAT==1 and mode fault detection is enabled (MR.MODFDIS==0), the SPI module will not start a data transfer. Fix/Workaround Disable mode fault detection by writing a one to MR.MODFDIS. Disabling SPI has no effect on the SR.TDRE bit Disabling SPI has no effect on the SR.
AT32UC3A3 Fix/Workaround Disable and then enable the peripheral after the transfer error. AES URAD (Unspecified Register Access Detection Status) does not detect read accesses to the write-only KEYW[5..8]R registers Fix/Workaround None. 39.3.5 HMATRIX In the PRAS and PRBS registers, the MxPR fields are only two bits In the PRAS and PRBS registers, the MxPR fields are only two bits wide, instead of four bits. The unused bits are undefined when reading the registers.
AT32UC3A3 39.3.8 SSC Frame Synchro and Frame Synchro Data are delayed by one clock cycle The frame synchro and the frame synchro data are delayed from 1 SSC_CLOCK when: - Clock is CKDIV - The START is selected on either a frame synchro edge or a level - Frame synchro data is enabled - Transmit clock is gated on output (through CKO field) Fix/Workaround Transmit or receive CLOCK must not be gated (by the mean of CKO field) when START condition is performed on a generated frame synchro. 39.3.
AT32UC3A3 40. Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 40.1 40.2 40.3 40.4 40.5 40.6 Rev. H– 10/12 1. Updated max frequency 2. Added Flash Read High Speed Mode description in FLASHC chapter 3. Updated Electrical Characteristics accordingly to new max frequency 4. Fixed wrong description of PLLOPT[0] in PM chapter 5.
AT32UC3A3 40.7 40.8 Rev. B – 08/09 1. Updated the datasheet with new device AT32UC3A4. 1. Initial revision. Rev.
AT32UC3A3 Table of Contents 1 Description ............................................................................................... 3 2 Overview ................................................................................................... 4 3 4 5 6 7 2.1 Block Diagram ...................................................................................................4 2.2 Configuration Summary .....................................................................................
AT32UC3A3 8 9 Real Time Counter (RTC) ...................................................................... 80 8.1 Features ..........................................................................................................80 8.2 Overview ..........................................................................................................80 8.3 Block Diagram .................................................................................................80 8.4 Product Dependencies ....
AT32UC3A3 12.4 Functional description ....................................................................................131 12.5 Flash commands ...........................................................................................134 12.6 General-purpose fuse bits .............................................................................136 12.7 Security bit .....................................................................................................138 12.8 User interface .......
AT32UC3A3 16.4 I/O Lines Description .....................................................................................220 16.5 Application Example ......................................................................................221 16.6 Product Dependencies ..................................................................................222 16.7 Functional Description ...................................................................................223 16.8 User Interface ...............
AT32UC3A3 19.13 Module Configuration ....................................................................................380 20 General-Purpose Input/Output Controller (GPIO) ............................. 381 20.1 Features ........................................................................................................381 20.2 Overview ........................................................................................................381 20.3 Block Diagram .................................
AT32UC3A3 23.4 Block Diagram ...............................................................................................475 23.5 Application Block Diagram .............................................................................476 23.6 I/O Lines Description .....................................................................................476 23.7 Product Dependencies ..................................................................................476 23.8 Functional Description .......
AT32UC3A3 27.7 Functional Description ...................................................................................630 27.8 User Interface ................................................................................................665 27.9 Module Configuration ....................................................................................748 28 Timer/Counter (TC) .............................................................................. 749 28.1 Features ...........................
AT32UC3A3 31.6 Functional Description ...................................................................................823 31.7 User Interface ................................................................................................841 31.8 Module Configuration ....................................................................................869 32 Memory Stick Interface (MSI) .............................................................. 870 32.1 Features .................................
AT32UC3A3 36.2 DC Characteristics .........................................................................................961 36.3 I/O pin Characteristics ...................................................................................962 36.4 Regulator characteristics ...............................................................................963 36.5 Analog characteristics ...................................................................................964 36.6 Power Consumption ........
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