Datasheet

5
AT32UC3A
4. Blockdiagram
Figure 4-1. Blockdiagram
UC CPU
NEXUS
CLASS 2+
OCD
INSTR
INTERFACE
DATA
INTERFACE
TIMER/COUNTER
INTERRUPT
CONTROLLER
REAL TIME
COUNTER
PERIPHERAL
DMA
CONTROLLER
512 KB
FLASH
HSB-PB
BRIDGE B
HSB-PB
BRIDGE A
MEMORY INTERFACE
S
MM M
M
M
S
S
S
S
S
M
EXTERNAL
INTERRUPT
CONTROLLER
HIGH SPEED
BUS MATRIX
FAST GPIO
GENERAL PURPOSE IOs
64 KB
SRAM
GENERAL PURPOSE IOs
PA
PB
PC
PX
A[2..0]
B[2..0]
CLK[2..0]
EXTINT[7..0]
KPS[7..0]
NMI_N
GCLK[3..0]
XIN32
XOUT32
XIN0
XOUT0
PA
PB
PC
PX
RESET_N
EXTERNAL BUS INTERFACE
(SDRAM & STATIC MEMORY
CONTROLLER)
CAS
RAS
SDA10
SDCK
SDCKE
SDCS0
SDWE
NCS[3..0]
NRD
NWAIT
NWE0
DATA[15..0]
USB
INTERFACE
DMA
ID
VBOF
VBUS
D-
D+
ETHERNET
MAC
DMA
32 KHz
OSC
115 kHz
RCOSC
OSC0
PLL0
PULSE WIDTH
MODULATION
CONTROLLER
SERIAL
PERIPHERAL
INTERFACE 0/1
TWO-WIRE
INTERFACE
PDCPDC PDC
MISO, MOSI
NPCS[3..1]
PWM[6..0]
SCL
SDA
USART1
PDC
RXD
TXD
CLK
RTS, CTS
DSR, DTR, DCD, RI
USART0
USART2
USART3
PDC
RXD
TXD
CLK
RTS, CTS
SYNCHRONOUS
SERIAL
CONTROLLER
PDC
TX_CLOCK, TX_FRAME_SYNC
RX_DATA
TX_DATA
RX_CLOCK, RX_FRAME_SYNC
ANALOG TO
DIGITAL
CONVERTER
PDC
AD[7..0]
ADVREF
WATCHDOG
TIMER
XIN1
XOUT1
OSC1
PLL1
SCK
JTAG
INTERFACE
MCKO
MDO[5..0]
MSEO[1..0]
EVTI_N
EVTO_N
TCK
TDO
TDI
TMS
POWER
MANAGER
RESET
CONTROLLER
ADDR[23..0]
SLEEP
CONTROLLER
CLOCK
CONTROLLER
CLOCK
GENERATOR
COL,
CRS,
RXD[3..0],
RX_CLK,
RX_DV,
RX_ER
MDC,
TXD[3..0],
TX_CLK,
TX_EN,
TX_ER,
SPEED
MDIO
FLASH
CONTROLLER
CONFIGURATION REGISTERS BUS
MEMORY PROTECTION UNIT
PB
PB
HSB
HS
B
NWE1
NWE3
PBA
PBB
NPCS0
LOCAL BUS
INTERFACE
AUDIO
BITSTREAM
DAC
PDC
DATA[1..0]
DATAN[1..0]
32058KS–AVR32–01/12