Datasheet

60
AT32UC3A
Notes: 1. 3.3V domain: V
VDDIO
from 3.0V to 3.6V, maximum external capacitor = 40 pF.
2. t
CPMCK
: Master Clock period in ns.
12.12 MACB Characteristics
Notes: 1. f: MCK frequency (MHz)
2. V
VDDIO
from 3.0V to 3.6V, maximum external capacitor = 20 pF
Table 12-30. SPI Timings
Symbol Parameter Conditions Min Max Units
SPI
0
MISO Setup time before SPCK rises (master) 3.3V domain
(1)
22 + (t
CPMCK
)/2
(2)
ns
SPI
1
MISO Hold time after SPCK rises (master) 3.3V domain
(1)
0ns
SPI
2
SPCK rising to MOSI Delay (master) 3.3V domain
(1)
7ns
SPI
3
MISO Setup time before SPCK falls (master) 3.3V domain
(1)
22 + (t
CPMCK
)/2
(2)
ns
SPI
4
MISO Hold time after SPCK falls (master) 3.3V domain
(1)
0ns
SPI
5
SPCK falling to MOSI Delay (master) 3.3V domain
(1)
7ns
SPI
6
SPCK falling to MISO Delay (slave) 3.3V domain
(1)
26.5 ns
SPI
7
MOSI Setup time before SPCK rises (slave) 3.3V domain
(1)
0ns
SPI
8
MOSI Hold time after SPCK rises (slave) 3.3V domain
(1)
1.5 ns
SPI
9
SPCK rising to MISO Delay (slave) 3.3V domain
(1)
27 ns
SPI
10
MOSI Setup time before SPCK falls (slave) 3.3V domain
(1)
0ns
SPI
11
MOSI Hold time after SPCK falls (slave) 3.3V domain
(1)
1ns
Table 12-31. Ethernet MAC Signals
Symbol Parameter Conditions Min (ns) Max (ns)
EMAC
1
Setup for EMDIO from EMDC rising Load: 20pF
(2)
EMAC
2
Hold for EMDIO from EMDC rising Load: 20pF
(2)
EMAC
3
EMDIO toggling from EMDC falling Load: 20pF
(2)
Table 12-32. Ethernet MAC MII Specific Signals
Symbol Parameter Conditions Min (ns) Max (ns)
EMAC
4
Setup for ECOL from ETXCK rising Load: 20pF
(1)
3
EMAC
5
Hold for ECOL from ETXCK rising Load: 20pF
(1)
0
EMAC
6
Setup for ECRS from ETXCK rising Load: 20pF
(1)
3
EMAC
7
Hold for ECRS from ETXCK rising Load: 20pF
(1)
0
EMAC
8
ETXER toggling from ETXCK rising Load: 20pF
(1)
15
EMAC
9
ETXEN toggling from ETXCK rising Load: 20pF
(1)
15
EMAC
10
ETX toggling from ETXCK rising Load: 20pF
(1)
15
EMAC
11
Setup for ERX from ERXCK Load: 20pF
(1)
1
32058KS–AVR32–01/12