Datasheet
Table Of Contents
- Features
- Temperature Sensor Features
- Serial EEPROM Features
- Table of Contents
- 1. Description
- 2. Pin Descriptions and Pinouts
- 3. Block Diagram
- 4. Device Communication
- 5. Device Addressing
- 6. Temperature Sensor
- 6.1 Functional Description
- 6.2 Register Descriptions
- 6.2.1 Pointer Register (8-bit Write Only, Address = N/A)
- 6.2.2 Capability Register (16-bit Read-only, Address = 00h)
- 6.2.3 Configuration Register (16-bit Read/Write, Address = 01h)
- 6.2.4 Upper Limit Register (16-bit Read/Write, Address = 02h)
- 6.2.5 Lower Limit Register (16-bit Read/Write, Address = 03h)
- 6.2.6 Critical Alarm Register (16-bit Read/Write, Address = 04h)
- 6.2.7 Temperature Register (16-bit Read-only, Address = 05h)
- 6.2.8 Manufacturer ID Register (16-bit Read-only, Address = 06h)
- 6.2.9 Device ID Register (16-bit Read-only, Address = 07h)
- 6.3 Temperature Sensor Write Operations
- 6.4 Temperature Sensor Read Operations
- 7. Serial EEPROM
- 8. Electrical Specifications
- 9. Ordering Code Detail
- 10. Ordering Information
- 11. Part Markings
- 12. Package Drawings
- 13. Revision History
AT30TSE004A [DATASHEET]
Atmel-8868C-DTS-AT30TSE004A-Datasheet_122013
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7.4.3 Sequential Read
A Sequential Read operation is initiated in the same way as a Random Read operation, except after the
AT30TSE004A transmits the first data word, the Master responds with an ACK (instead of a NACK followed by
a Stop condition). As long as the AT34TSE004A receives an ACK, it will continue to increment the data word
address and serially clock out the sequential data words (see Figure 7-11). When the internal address counter is
at the last byte of the last page, the data word address will roll-over to the beginning of the selected 2-Kbit array
(depending on the SPA setting) starting at address zero, and the Sequential Read operation will continue. The
Sequential Read operation is terminated when the Master responds with a NACK followed by a Stop condition.
Figure 7-11. Sequential Read from Serial EEPROM
SCL
SDA
Start
by
Master
ACK
from
Slave
ACK
from
Master
Device Address Byte Data Word (n)
MSB MSB
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
1 0 1 0 A2 A1
A0 1 0 D7 D6 D5 D4 D3 D2 D1 D0 0
ACK
from
Master
NACK
from
Master
Stop
by
Master
ACK
from
Master
Data Word (n+1) Data Word (n+2)
Data Word (n+x)
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
D7 D6 D5 D4 D3 D2 D1 D0 0 D7 D6 D5 D4 D3 D2 D1 D0 0 D7 D6 D5 D4 D3 D2 D1 D0 1
MSB MSB MSB