Datasheet
Table Of Contents
- Features
- Temperature Sensor Features
- Serial EEPROM Features
- Table of Contents
- 1. Description
- 2. Pin Descriptions and Pinouts
- 3. Block Diagram
- 4. Device Communication
- 5. Device Addressing
- 6. Temperature Sensor
- 6.1 Functional Description
- 6.2 Register Descriptions
- 6.2.1 Pointer Register (8-bit Write Only, Address = N/A)
- 6.2.2 Capability Register (16-bit Read-only, Address = 00h)
- 6.2.3 Configuration Register (16-bit Read/Write, Address = 01h)
- 6.2.4 Upper Limit Register (16-bit Read/Write, Address = 02h)
- 6.2.5 Lower Limit Register (16-bit Read/Write, Address = 03h)
- 6.2.6 Critical Alarm Register (16-bit Read/Write, Address = 04h)
- 6.2.7 Temperature Register (16-bit Read-only, Address = 05h)
- 6.2.8 Manufacturer ID Register (16-bit Read-only, Address = 06h)
- 6.2.9 Device ID Register (16-bit Read-only, Address = 07h)
- 6.3 Temperature Sensor Write Operations
- 6.4 Temperature Sensor Read Operations
- 7. Serial EEPROM
- 8. Electrical Specifications
- 9. Ordering Code Detail
- 10. Ordering Information
- 11. Part Markings
- 12. Package Drawings
- 13. Revision History
27
AT30TSE004A [DATASHEET]
Atmel-8868C-DTS-AT30TSE004A-Datasheet_122013
Figure 7-1. Set Page Address (SPA)
Reading the state of the SPA can be accomplished via the Read Page Address (RPA) command. The Master
can issue the RPA command to determine if the AT30TSE004A’s internal address counter is located in the first
2-Kbit section or the second 2-Kbit memory section based upon the device’s ACK or NACK response to the
RPA command.
The RPA command sequence requires the Master to transmit a Start condition followed by a control byte of
‘01101101’(6Dh). The device’s current address counter (page address) is located in the first half of the
memory if the AT30TSE004A responds with an ACK to the RPA command. Alternatively, if the device’s
response to the RPA command is a NACK, indicates the page address is located in the second half of the
memory (see Figure 7-2). Following the control byte and the device’s ACK or NACK response, the
AT30TSE004A should transmit two data bytes of don’t care values. The Master should NACK on these two data
bytes followed by the Master sending a Stop condition to end the operation.
After power-up, the SPA is set to zero indicating internal address counter is located in the first half of the
memory. Performing a software reset (see Section 4.8 “2-wire Software Reset” on page 10) will also set the
SPA to zero.
The AT30TSE004A incorporates a Reversible Software Write Protect (RSWP) feature that allows the ability to
selectively write protect data stored in any or all of the four Serial EEPROM 128-byte quadrants. See
Section 7.3 “Write Protection” on page 33 for more information on the RSWP feature.
Figure 7-2. Read Page Address (RPA)
SCL
SDA
Start
by
Master
ACK
from
Slave
NACK
from
Slave
Stop
by
Master
NACK
from
Slave
Control Byte Most Significant Data Byte Least Significant Data Byte
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
0 1 1 0 1 1 * 0 0 X X X X X X X X 1 X X X X X X X X 1
MSB MSB MSB
Bit * = 1: Indicates the page address is located in the second half of the memory.
Bit * = 0: Indicates the page address is located in the first half of the memory.
SCL
SDA
Start
by
Master
ACK or NACK
from
Slave
NACK
from
Master
Stop
by
Master
NACK
from
Master
Control Byte Most Significant Data Byte Least Significant Data Byte
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
0 1 1 0 1 1 0 1 * X X X X X X X X 1 X X X X X X X X 1
MSB MSB MSB
Bit * = 1: NACK indicates the device’s internal address counter is located in the second half of the memory.
Bit * = 0: ACK indicates the device’s internal address counter is located in the first half of the memory.