Datasheet
Table Of Contents
- Features
- Temperature Sensor Features
- Serial EEPROM Features
- Table of Contents
- 1. Description
- 2. Pin Descriptions and Pinouts
- 3. Block Diagram
- 4. Device Communication
- 5. Device Addressing
- 6. Temperature Sensor
- 6.1 Functional Description
- 6.2 Register Descriptions
- 6.2.1 Pointer Register (8-bit Write Only, Address = N/A)
- 6.2.2 Capability Register (16-bit Read-only, Address = 00h)
- 6.2.3 Configuration Register (16-bit Read/Write, Address = 01h)
- 6.2.4 Upper Limit Register (16-bit Read/Write, Address = 02h)
- 6.2.5 Lower Limit Register (16-bit Read/Write, Address = 03h)
- 6.2.6 Critical Alarm Register (16-bit Read/Write, Address = 04h)
- 6.2.7 Temperature Register (16-bit Read-only, Address = 05h)
- 6.2.8 Manufacturer ID Register (16-bit Read-only, Address = 06h)
- 6.2.9 Device ID Register (16-bit Read-only, Address = 07h)
- 6.3 Temperature Sensor Write Operations
- 6.4 Temperature Sensor Read Operations
- 7. Serial EEPROM
- 8. Electrical Specifications
- 9. Ordering Code Detail
- 10. Ordering Information
- 11. Part Markings
- 12. Package Drawings
- 13. Revision History
AT30TSE004A [DATASHEET]
Atmel-8868C-DTS-AT30TSE004A-Datasheet_122013
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7. Serial EEPROM
7.1 Memory Organization
To provide the greatest flexibility and backwards compatibility with the previous generations of SPD devices, the
AT30TSE004A memory organization is organized into two independent 2-Kbit memory arrays. Each 2-Kbit
(256-byte) section is internally organized into two independent quadrants of 128 bytes with each quadrant
comprised of eight pages of 16 bytes. Including both memory sections, there are four 128-byte quadrants
totaling 512 bytes. The Memory Array organization details are shown in Section on page 6 and Table 7-1.
7.1.1 Set Page Address and Read Page Address Commands
The AT30TSE004A incorporates an innovative memory addressing technique that utilizes a Set Page Address
(SPA) and Read Page Address (RPA) commands to select and verify the desired half of the memory is enabled
to perform Write and Read operations.
Example: If SPA = 0, then the first-half or lower 256 bytes of the Serial EEPROM is selected allowing
access to Quadrant 0 and Quadrant 1. Alternately, if SPA = 1, then the second-half or upper 256
bytes of the Serial EEPROM is selected allowing access to Quadrant 2 and Quadrant 3.
Table 7-1. Set Page Address and Memory Organization
Note: Due to the requirement for the A
0
pin to be driven to V
HV
, the SPA and the RPA commands are fully supported in a
single DIMM (isolated DIMM) end application or a single DIMM programming station only.
Setting the Set Page Address (SPA) value selects the desired half of the EEPROM for performing Write or Read
operations. This is done by sending the SPA as seen in Figure 7-1. The SPA command sequence requires the
Master to transmit a Start condition followed by sending a control byte of ‘011011*0’ where the ‘*’ in the bit
7 position will dictate which half of the EEPROM is being addressed. A ‘0’ in this position (or 6Ch) is required
to set the page address to the first half of the memory and a ‘1’ (or 6Eh) is necessary to set the page address
to the second half of the memory. After receiving the control byte, the AT30TSE004A should return an ACK and
the Master should follow by sending two data bytes of don’t care values. The AT30TSE004A responds with a
NACK to each of these two data bytes although the JEDEC TSE2004av specification allows for either an ACK
or NACK response. The protocol is completed by the Master sending a Stop condition to end the operation.
Block Set Page Address (SPA) Memory Address Locations
Quadrant 0 0 00h to 7Fh
Quadrant 1 0 80h to FFh
Quadrant 2 1 00h to 7Fh
Quadrant 3 1 80h to FFh