Datasheet
Table Of Contents
- Features
- Temperature Sensor Features
- Serial EEPROM Features
- Table of Contents
- 1. Description
- 2. Pin Descriptions and Pinouts
- 3. Block Diagram
- 4. Device Communication
- 5. Device Addressing
- 6. Temperature Sensor
- 6.1 Functional Description
- 6.2 Register Descriptions
- 6.2.1 Pointer Register (8-bit Write Only, Address = N/A)
- 6.2.2 Capability Register (16-bit Read-only, Address = 00h)
- 6.2.3 Configuration Register (16-bit Read/Write, Address = 01h)
- 6.2.4 Upper Limit Register (16-bit Read/Write, Address = 02h)
- 6.2.5 Lower Limit Register (16-bit Read/Write, Address = 03h)
- 6.2.6 Critical Alarm Register (16-bit Read/Write, Address = 04h)
- 6.2.7 Temperature Register (16-bit Read-only, Address = 05h)
- 6.2.8 Manufacturer ID Register (16-bit Read-only, Address = 06h)
- 6.2.9 Device ID Register (16-bit Read-only, Address = 07h)
- 6.3 Temperature Sensor Write Operations
- 6.4 Temperature Sensor Read Operations
- 7. Serial EEPROM
- 8. Electrical Specifications
- 9. Ordering Code Detail
- 10. Ordering Information
- 11. Part Markings
- 12. Package Drawings
- 13. Revision History
AT30TSE004A [DATASHEET]
Atmel-8868C-DTS-AT30TSE004A-Datasheet_122013
16
7 CRTALML
Crit_Alarm Lock bit:
0 = The Crit_Alarm Register can be updated (power-on default).
1 = The Crit_Alarm Register is locked and cannot be updated.
This bit locks the Critical Alarm Register from being updated.
Once set, it can only be cleared to a Logic 0 by an internal Power-On Reset.
6 WINLOCK
Alarm Window Lock bit:
0 = The Upper Limit and Lower Limit Registers can be updated (power-on default).
1 = The Upper and Lower Limit Registers are locked and cannot be updated.
Once set, it can be only be cleared to a Logic 0 by an internal Power-On Reset.
5 EVTCLR
EVENT Clear:
0 = Has no effect (power-on default).
1 = Clears (releases) the active
EVENT
pin in Interrupt Mode.
This bit will clear the
EVENT
pin after it has been enabled. This bit is a
write-only bit and will read as a Logic 0 and is ignored when in Comparator Mode.
4 EVTSTS
EVENT
Pin Output Status:
0 = The
EVENT output is not asserted by the device (power-on default).
1 = The
EVENT output is asserted due to a limit or alarm condition.
3 EVTOUT
EVENT
Output Control:
0 = The
EVENT
output is disabled and will not generate interrupts (power-on default).
1 = The
EVENT
output is enabled.
This bit cannot be altered if the Crit_Alarm or the Alarm Window Lock bits is set.
2 CRITEVT
Critical Temperature only:
0 = The
EVENT
output is asserted if the measured temperature is above the Upper Limit or
Critical Alarm, or is below the Lower Limit (power-on default).
1 = The
EVENT
output is asserted only for a Critical Alarm violation when the temperature is
greater then the Crit_Alarm.
This bit cannot be altered if the Alarm Window Lock bit is set.
1 EVTPOL
EVENT
Polarity:
0 = The
EVENT
pin is active low (power-on default).
1 = The
EVENT
pin is active high.
This bit cannot be altered if the Crit_Alarm or the Alarm Window Lock bit is set.
A pull-up resistor is required on this pin to achieve the Logic 1 state.
0 EVTMOD
EVENT
Mode:
0 = The
EVENT
pin will operate in Comparator Mode (power-on default).
1 = The
EVENT
pin will operate in Interrupt Mode.
This bit cannot be altered if the Crit_Alarm or the Alarm Window Lock bit is set.
Table 6-6. Configuration Register Bit Description (Continued)
Bit Symbol Description