Datasheet

Table Of Contents
35
AT30TSE004A [DATASHEET]
Atmel-8868C-DTS-AT30TSE004A-Datasheet_122013
7.4.1 Current Address Read
Following a Start condition, the Master only transmits the device address byte with the R/W select bit set to a
Logic 1 (see Figure 7-9). The AT30TSE004A should respond with an ACK and then serially transmits the data
word addressed by the internal address counter. The internal data word address counter maintains the last
address accessed during the last Read or Write operation, incremented by one. This address stays valid
between operations as long as power to the device is maintained. The address roll-over during a Read is from
the last byte of the last page to the first byte of the first page of the addressed 2-Kbit (depends on the current
SPA setting). To end the command, the Master does not respond with an ACK but does generate a following
Stop condition.
Figure 7-9. Current Address Read from Serial EEPROM
7.4.2 Random Read
A Random Read operation allows the Master to access any memory location in a random manner and requires
a dummy write sequence to preload the starting data word address. To perform a Random Read, the device
address byte and the word address byte are transmitted to the AT30TSE004A as part of the dummy Write
sequence (see Figure 7-10). Once the device address byte and data word address are clocked in and
acknowledged by the AT30TSE004A, the Master must generate another Start condition. The Master initiates a
Current Address Read by sending another device address byte with the R/W select bit to a Logic 1. The
AT30TSE004A acknowledges the device address byte, increments its internal address counter and serially
clocks out the first data word. The device will continue to transmit sequential data words as long as the Master
continues to ACK each data word. To end the sequence, the Master responds with a NACK and a Stop
condition.
Figure 7-10. Random Read from Serial EEPROM
SCL
SDA
Device Address Byte
Data Word (n)
Start
by
Master
ACK
from
Slave
NACK
from
Master
Stop
by
Master
MSB MSB
1 0 1 0 A2 A1 A0 1 0 D7 D6 D5 D4 D3 D2 D1 D0 1
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
SCL
SDA
Start
by
Master
ACK
from
Slave
ACK
from
Slave
Device Address Byte Word Address Byte
MSB MSB
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
1 0 1 0 A2 A1 A0 0 0 0
Dummy Write
Start
by
Master
ACK
from
Slave
NACK
from
Master
Device Address Byte
Data Word (n)
Stop
by
Maste
r
MSB MSB
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
1 0 1 0 A2 A1 A0 1 0 D7 D6 D5 D4 D3 D2 D1 D0 1
A7 A6 A5 A4 A3 A2 A1 A0