Datasheet

Table Of Contents
29
AT30TSE004A [DATASHEET]
Atmel-8868C-DTS-AT30TSE004A-Datasheet_122013
7.2.1 Byte Write
Following the Start condition from the Master, the device type identifier (‘1010’), the device address bits and
the R/W select bit (set to a Logic 0) are clocked onto the bus by the Master (see Figure 7-3). This indicates to
the addressed device that the Master will follow by transmitting a byte with the word address. The
AT30TSE004A will respond with an ACK during the ninth clock cycle. Then the next byte transmitted by the
Master is the 8-bit word address of the byte location to be written into the Serial EEPROM. After receiving an
ACK from the AT30TSE004A, the Master transmits the data word to be programmed followed by an ACK from
the AT30TSE004A. The Master ends the Write sequence with a Stop condition during the 10
th
clock cycle to
initiate the internally self-timed write cycle. A Stop condition issued during any other clock cycle during the Write
operation will not trigger the internally self-timed write cycle. Once the write cycle begins, the pre-loaded data
word will be programmed in the amount of time not to exceed the t
WR
specification. The t
WR
time is defined in
more detail in Section 7.2.4 on page 32. During this time, the Master should wait a fixed amount of time set to
the t
WR
specification, or for time sensitive applications, an ACK polling routine can be implemented (see
Figure 7-5 on page 32). All inputs are ignored by the Serial EEPROM during the write cycle and the Serial
EEPROM will not respond until the write cycle is complete. The Serial EEPROM will increment its internal
address counter each time a byte is written.
Note: The temperature sensor operations can be accessed during the write cycle to read the Temperature Register or
perform any other temperature sensor function.
Figure 7-3. Byte Write to Serial EEPROM
SCL
SDA
Device Address Byte Word Address Byte Data Word
Start
by
Master
ACK
from
Slave
ACK
from
Slave
MSB
MSB
ACK
from
Slave
Stop
by
Maste
r
MSB
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
1 0 1 0 A2 A1 A0 0 0 A7 A6 A5 A4 A3 A2 A1 A0 0 D7 D6 D5 D4 D3 D2 D1 D0 0