AT30TSE004A Integrated Temperature Sensor with Serial EEPROM DATASHEET Features Integrated Temperature Sensor (TS) + 4-Kbit Serial EEPROM JEDEC JC42.4 (TSE2004av) DIMM Serial Presence Detect (SPD) + TS compliant Low voltage operation ̶ Optimized for VCC range of 1.7V to 3.
T a b l e o f C o n te n ts 1. Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2. Pin Descriptions and Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4.
7.4 8. 34 35 35 36 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 8.1 8.2 8.3 8.4 8.5 9. Serial EEPROM Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4.1 Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4.2 Random Read . . . . . . . . . . . . . . . . . . . . . .
1. Description The Atmel® AT30TSE004A is a combination Serial EEPROM and temperature sensor device containing 4096bits of Serially Electrically Erasable and Programmable Read-Only Memory (EEPROM) organized as 512-bytes of eight bits each. The Serial EEPROM operation is tailored specifically for DRAM memory modules with Serial Presence Detect (SPD) to store a module’s vital product data such as the module’s size, speed, voltage, data width, and timing parameters.
2. Pin Descriptions and Pinouts Table 2-1. Pin Descriptions Symbol Name and Function SCL Serial Clock: The SCL pin is used to provide a clock to the device and is used to control the flow of data to and from the device. Command and input data present on the SDA pin is always latched in on the rising edge of SCL, while output data on the SDA pin is always clocked out on the falling edge of SCL.
3. Block Diagram Serial EEPROM Temperature Sensor Selected Resolution Temp. Range H.
4. Device Communication The AT30TSE004A operates as a slave device and utilizes a simple 2-wire digital serial interface, compatible with the I2C Fast Mode Plus (I2C FM+) protocol, to communicate with a host controller, commonly referred to as the bus Master. The Master initiates and controls all Read and Write operations to the slave devices on the serial bus, and both the Master and the slave devices can transmit and receive data on the bus.
4.4 No-Acknowledge (NACK) When the AT30TSE004A is transmitting data to the Master, the Master can indicate that it is done receiving data and wants to end the operation by sending a NACK response to the AT30TSE004A instead of an ACK response. This is accomplished by the Master outputting a Logic 1 during the ACK/NACK clock cycle, at which point the AT30TSE004A will release the SDA line so that the Master can then generate a Stop condition.
Table 6-1 on page 13 shows the power-on register default values. The Upper Limit, Lower Limit, Critical Alarm, and Configuration Registers should be programmed to their user desired values before the temperature sensor can properly function. Before selecting the device and issuing protocol, a valid and stable supply voltage must be applied and no protocol should be issued to the device for the time specified by the tINIT parameter.
4.7 Timeout The AT30TSE004A supports the industry standard bus Timeout feature on both temperature sensor and Serial EEPROM operations to help prevent potential system bus hang-ups. The device resets its serial interface and will stop driving the bus (will let SDA float high) if the SCL pin is held low for more than the minimum Timeout (tOUT) specification. The AT30TSE004A will be ready to accept a new Start condition before the maximum tOUT has elapsed (see Figure 4-3).
5. Device Addressing The AT30TSE004A is designed to allow the Serial EEPROM and the temperature sensor to operate in parallel while executing valid command protocol. For example, when the temperature sensor is busy during a temperature conversion cycle, it is possible to perform any Serial EEPROM operation during this time and vice versa.
6. Temperature Sensor 6.1 Functional Description The temperature sensor consists of a Delta-Sigma Analog to Digital Converter (ADC) with a band gap type temperature sensor that monitors and updates its temperature measurement at least eight times per second converting the temperature readings into digital data bits and latching them into the Temperature Register that can be read via the 2-wire I2C FM+ serial interface.
Table 6-1. Registers Register Address Read/Write Section Power-On Default Pointer Register n/a W 6.2.1 00h Capability Register 00h R 6.2.2 00F7h Configuration Register 01h R/W 6.2.3 0000h Upper Limit Register 02h R/W 6.2.4 0000h Lower Limit Register 03h R/W 6.2.5 0000h Critical Alarm Register 04h R/W 6.2.6 0000h Temperature Register 05h R 6.2.7 N/A Manufacturer I.D. Register 06h R 6.2.8 1114h Device I.D./Device Revision Register 07h R 6.2.
6.2.2 Capability Register (16-bit Read-only, Address = 00h) This register is a 16-bit read-only register used to specify the functional capabilities of the temperature sensor. The AT30TSE004A is capable of measuring temperature with ±1C over the active range and ±2C over the monitor range. The Capability Register functions are described in Table 6-3 and Table 6-4. Table 6-3.
6.2.3 Configuration Register (16-bit Read/Write, Address = 01h) The AT30TSE004A incorporates a 16-bit Configuration Register allowing the user to set key operational features of the temperature sensor. The Configuration Register functions are described in Table 6-5 and Table 6-6. Table 6-5.
Table 6-6. Bit Configuration Register Bit Description (Continued) Symbol Description Crit_Alarm Lock bit: 0 = The Crit_Alarm Register can be updated (power-on default). 7 CRTALML 1 = The Crit_Alarm Register is locked and cannot be updated. This bit locks the Critical Alarm Register from being updated. Once set, it can only be cleared to a Logic 0 by an internal Power-On Reset. Alarm Window Lock bit: 6 WINLOCK 0 = The Upper Limit and Lower Limit Registers can be updated (power-on default).
Figure 6-1.
6.2.4 Upper Limit Register (16-bit Read/Write, Address = 02h) The Upper Limit Register holds the user programmed upper temperature boundary trip point in 2’s complement format (0.125C resolution) that can be utilized to monitor the temperature in an operating window between the Upper Limit Register and the Lower Limit Register settings (see Table 6-7 and Table 6-9).
6.2.5 Lower Limit Register (16-bit Read/Write, Address = 03h) The Lower Limit Register holds the user programmed lower temperature boundary trip point in 2’s complement format (0.125C resolution) that can be utilized to monitor the temperature in an operating window (see Table 6-7 and Table 6-9). When the temperature decreases below this trip point minus any hysteresis set or increases to meet or exceed this trip point, then the EVENT pin is asserted (if enabled).
6.2.6 Critical Alarm Register (16-bit Read/Write, Address = 04h) The Critical Alarm Register holds the user programmed Critical Alarm temperature boundary trip point in 2’s complement format (0.125°C resolution) that can be utilized to monitor the temperature (see Table 6-11 and Table 6-12). When the temperature increases above this trip point, the EVENT pin will be asserted (if enabled). It will remain asserted until temperature decreases below or equal to the trip point minus any hysteresis set.
6.2.7 Temperature Register (16-bit Read-only, Address = 05h) The Temperature Register holds the internal temperature measurement data represented in 2’s complement format allowing for resolution equal to 0.125C (least significant bit). The upper three bits (15, 14, and 13) of the Temperature Register indicates the trip status of the current temperature and most important, are not affected by the status of the output of the EVENT pin (see Table 6-13 and Table 6-14). Table 6-13.
6.2.7.1 Temperature Register Format This section will clarify the Temperature Register format and temperature bit value assignments utilized for temperature for the following registers: Upper Limit, Lower Limit, Critical Alarm, and Temperature Registers. The temperatures expressed in the Upper Limit, Lower Limit, Critical Alarm, and Temperature Registers are indicated in 2’s complement format.
6.2.8 Manufacturer ID Register (16-bit Read-only, Address = 06h) The Manufacturer ID Register contains the PCI SIG number assigned to Atmel (1114h) as shown in Table 6-17. Table 6-17. Manufacturer ID Register Bit Distribution Bit 15 Bit 14 Bit 13 Bit 12 Symbol Bit 10 Bit 9 Bit 8 Manufacturer ID Default Value 0 0 0 1 0 0 0 1 R/W Access R R R R R R R R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Symbol 6.2.
6.3 Temperature Sensor Write Operations Writing to the Temperature Register of the AT30TSE004A is accomplished through a modified Write operation for two data bytes. To maintain 2-wire compatibility, the 16-bit registers are accessed through a Pointer Register requiring the TS Write sequence to include a Pointer Register byte following the device address byte to write the two data bytes. Figure 6-2 illustrates the entire Write transaction. Figure 6-2.
6.4 Temperature Sensor Read Operations Reading data from the temperature sensor may be accomplished in one of two ways: If the location latched in the Pointer Register is correct (for normal operation, it is expected the same address will be read repeatedly to read the temperature from the Temperature Register), the Register Pointer Word Read sequence should be utilized as shown in Figure 6-3.
7. Serial EEPROM 7.1 Memory Organization To provide the greatest flexibility and backwards compatibility with the previous generations of SPD devices, the AT30TSE004A memory organization is organized into two independent 2-Kbit memory arrays. Each 2-Kbit (256-byte) section is internally organized into two independent quadrants of 128 bytes with each quadrant comprised of eight pages of 16 bytes. Including both memory sections, there are four 128-byte quadrants totaling 512 bytes.
Figure 7-1. Set Page Address (SPA) 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 X 1 SCL Control Byte SDA 0 1 1 0 1 Most Significant Data Byte 1 * 0 0 MSB X X X X X X X Least Significant Data Byte X 1 MSB Start by Master X X X X X X X MSB ACK from Slave NACK from Slave NACK from Slave Stop by Master Bit * = 0: Indicates the page address is located in the first half of the memory.
7.2 Serial EEPROM Write Operations The 4-Kbit Serial EEPROM within the AT30TSE004A supports single Byte Write and Page Write operations up to the maximum page size of 16 bytes in one operation. The only difference between a Byte Write and a Page Write operation is the amount of data bytes loaded. Regardless of whether a Byte Write or Page Write operation is performed, the internally self-timed write cycle will take the same amount of time to write the data to the addressed memory location(s).
7.2.1 Byte Write Following the Start condition from the Master, the device type identifier (‘1010’), the device address bits and the R/W select bit (set to a Logic 0) are clocked onto the bus by the Master (see Figure 7-3). This indicates to the addressed device that the Master will follow by transmitting a byte with the word address. The AT30TSE004A will respond with an ACK during the ninth clock cycle.
7.2.2 Page Write The 4-Kbit Serial EEPROM is capable of writing up to 16 data bytes at a time executing the Page Write protocol sequence (see Figure 7-4). A partial or full Page Write operation is initiated the same as a Byte Write operation except that the Master does not send a Stop condition after the first data word is clocked in. Instead, after the Serial EEPROM has acknowledged receipt of the first data word, the Master can transmit up to fifteen more data words.
7.2.3 Acknowledge (ACK) Polling An ACK polling routine can be implemented to optimize time sensitive applications that would not prefer waiting the fixed maximum write cycle time and would prefer to know immediately when the Serial EEPROM write cycle has completed to start a subsequent operation.
7.3 Write Protection The AT30TSE004A incorporates a Reversible Software Write Protection (RSWP) feature that allows the ability to selectively write protect data stored in each of the four independent 128-byte Serial EEPROM quadrants. Table 7-3 identifies the memory quadrant identifier with its associated quadrant, SPA and memory address locations. The AT30TSE004A has three RSWP software commands: Set RSWP command for setting the RSWP.
Figure 7-7. Set RSWP and Clear RSWP 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 X X X 0/1 SCL Control Byte SDA 0 1 1 0 M Word Address Byte M M 0 0 MSB X X X X X X MSB Start by Master Data Word X X 0/1 X X X X X MSB Stop by ACK or NACK Master from Slave ACK or NACK from Slave ACK from Slave M = Memory Quadrant Identifier X = Don’t care 7.3.
Table 7-6. Read RSWP Control Byte Pin Function A2 A1 Read RSWP, Quadrant 0 X X Read RSWP, Quadrant 1 X X Read RSWP, Quadrant 2 X X Read RSWP, Quadrant 3 X X Notes: 1. 2. Memory Quadrant Identifier Device Type Identifier A0 B7 0, 1 or VHV B6 0 B5 1 B4 1 0 R/W B3 B2 B1 B0 0 0 1 1 1 0 0 1 1 0 1 1 0 0 0 1 X= Don’t care but recommend to be hard-wired to VCC or GND. See Section 8.2 for the VHV values. Figure 7-8.
7.4.1 Current Address Read Following a Start condition, the Master only transmits the device address byte with the R/W select bit set to a Logic 1 (see Figure 7-9). The AT30TSE004A should respond with an ACK and then serially transmits the data word addressed by the internal address counter. The internal data word address counter maintains the last address accessed during the last Read or Write operation, incremented by one.
7.4.3 Sequential Read A Sequential Read operation is initiated in the same way as a Random Read operation, except after the AT30TSE004A transmits the first data word, the Master responds with an ACK (instead of a NACK followed by a Stop condition). As long as the AT34TSE004A receives an ACK, it will continue to increment the data word address and serially clock out the sequential data words (see Figure 7-11).
8. Electrical Specifications 8.1 Absolute Maximum Ratings* *Notice: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the device at these ratings or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
8.3 AC Characteristics Applicable over recommended operating range: TAI = -20°C to +125°C, VCC = 1.7V to 3.6V, CL = 1 TTL Gate and 100μF (unless otherwise noted). VCC < 2.2V 100kHz VCC ≥ 2.
8.4 Temperature Sensor Characteristics Applicable over recommended operating range: TAI = -20°C to +125°C, VCC = 1.7V to 3.6V (unless otherwise noted). Freq. ≤ 400kHz 8.5 Symbol Parameter TACC TS Accuracy (B-grade) Test Condition Min Freq. > 400kHz Typ Max +75°C < Ta < +95°C ±0.5 +40°C < Ta < +125°C -20°C < Ta < +125°C Typ Max Units ±1.0 ±0.5 ±1.0 °C ±1.0 ±2.0 ±1.0 ±2.0 °C ±2.0 ±3.0 ±2.0 ±3.0 °C 125.0 75.0 125.0 ms TCONV TS Conversion Time 75.0 TRES TS Resolution 0.
9. Ordering Code Detail AT 3 0 T S E 0 0 4 A - M A 5 M - T Atmel Designator Shipping Carrier Option B = Bulk (Tubes) T = Tape and Reel Product Family Voltage Option 30TSE = Digital Temperature Sensor with Integrated EEPROM M = 1.7V to 3.6V Sensor Type Device Grade 5 = Green, NiPdAu Lead Finish Temperature Range (-20°C to +125°C) Device Density 4 = 4-kilobit Package Option MA = 8-lead, 2.0 x 3.0 x 0.6mm (UDFN) MAA = 8-lead, 2.0 x 3.0 x 0.8mm (WDFN) Device Revision 10.
11. Part Markings AT30TSE004A: Package Marking Information 8-lead UDFN 8-lead WDFN 2.0 x 3.0 mm Body 2.0 x 3.0 mm Body T8A 5M@ YXX Note 1: T8A 5M@ YXX Designates pin 1 Note 2: Package drawings are not to scale Catalog Number Truncation AT30TSE004A Truncation Code ###: T8A Date Codes Y = Year 2: 2012 3: 2013 4: 2014 5: 2015 Voltages 6: 2016 7: 2017 8: 2018 9: 2019 M = Month A: January B: February ... L: December WW = Work Week of Assembly 02: Week 2 04: Week 4 ...
12. Package Drawings 12.1 8MA2 — 8-pad UDFN E 1 8 Pin 1 ID 2 7 3 6 4 5 D C A2 A A1 E2 COMMON DIMENSIONS (Unit of Measure = mm) b (8x) 8 1 7 2 Pin#1 ID 6 D2 3 5 4 e (6x) K L (8x) SYMBOL MIN NOM MAX D 1.90 2.00 2.10 E 2.90 3.00 3.10 D2 1.40 1.50 1.60 E2 1.20 1.30 1.40 A 0.50 0.55 0.60 A1 0.0 0.02 0.05 A2 – – 0.55 C L NOTE 0.152 REF 0.30 e 0.35 0.40 0.50 BSC b 0.18 0.25 0.30 K 0.
12.2 8MAA — 8-pad WDFN TOP VIEW BOTTOM VIEW A D2 b (8X) Pin 1 Index Area E2 E Pin 1 ID L (8X) D A2 e (6X) A1 1.50 REF. A3 COMMON DIMENSIONS (Unit of Measure = mm) SIDE VIEW SYMBOL MIN NOM MAX A 0.70 0.75 0.80 A1 0.00 0.02 0.05 A2 0.45 0.55 0.65 A3 Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-229, WCED-3, for proper dimensions, tolerances, datums, etc. 2. Dimension b applies to metallized terminal and is measured between 0.15 mm and 0.
13. Revision History Doc. Rev. Date Comments 8868C 12/2013 Updated Section, “Power-up Conditions” and Figure, “Power-up Timing”. 8868B 07/2013 Updated the Absolute Maximum Ratings. 8868A 04/2013 Initial document release.
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