Datasheet

© 2011 Microchip Technology Inc. DS22284A-page 13
MCP16323
3.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
3.1 Switch Pin (SW)
The drain of the low-side N-Channel switch is
connected internally to the source of the high-side
N-Channel switch, and externally to the SW node
consisting of the inductor and bootstrap capacitor. The
SW node can rise very fast as a result of the internal
high-side switch turning on. It should be connected
directly to the 4.7 µH inductor with a wide, short trace.
3.2 Power Supply Input Voltage Pin
(V
IN
)
Connect the input voltage source to V
IN
. The input
source should be decoupled to GND using 2 x 10 µF
capacitors. The amount of the capacitance depends on
the impedance of the source and output current. The
input capacitors provide AC current for the high-side
power switch and a stable voltage source for the
internal device power. This capacitor should be
connected as close as possible to the V
IN
and GND
pins.
3.3 Signal Ground Pin (S
GND
)
This ground is used for the majority of the device,
including the analog reference, control loop, and other
circuits.
3.4 Feedback Voltage Pin (V
FB
)
The V
FB
input pin is used to provide output voltage reg-
ulation by either using a resistor divider or V
OUT
directly. For the adjustable version, the V
FB
will be 0.9V
typical with the output voltage in regulation. For the
fixed version, the V
FB
will be equal to the correspond-
ing V
OUT
value.
3.5 Power Good Pin (PG)
PG is an open drain, active low output. The regulator
output voltage is monitored and the PG line will remain
low until the output voltage reaches the V
OUT-UV
threshold. Once the internal comparator detects that
the output voltage is above the V
OUT-UV
threshold, an
internal delay timer is activated. After a 10 ms delay,
the PG open drain output pin can be pulled high,
indicating that the output voltage is in regulation. The
maximum voltage applied to the PG output pin should
not exceed 6V.
TABLE 3-1: PIN FUNCTION TABLE
MCP16323
3x3 QFN
Symbol Description
1 SW Output switch node, connects to the inductor and the bootstrap capacitor
2V
IN
Input supply voltage pin for power and internal biasing
3V
IN
Input supply voltage pin for power and internal biasing
4 SGND Primary signal ground
5V
FB
Output voltage feedback pin. Connect V
FB
to V
OUT
for fixed version and output
resistor divider for adjustable version.
6 NC No Connection
7 NC No Connection
8 PG Power Good open-drain output, pulled up to a maximum of 6V
9 EN Enable input pin. Logic high enables the operation. Internally pulled up, pull EN pin
low to disable regulator’s output. Maximum voltage on EN input is 6V.
10 BOOST Boost voltage that drives the internal NMOS control switch. A bootstrap capacitor
is connected between the BOOST and SW pins.
11 V
IN
Input supply voltage pin for power and internal biasing
12 SW Output switch node, connects to the inductor and the bootstrap capacitor
13 SW Output switch node, connects to the inductor and the bootstrap capacitor
14 PGND GND supply for the internal low-side NMOS/integrated diode
15 PGND GND supply for the internal low-side NMOS/integrated diode
16 SW Output switch node, connects to the inductor and the bootstrap capacitor
17 EP Exposed Thermal Pad (EP); must be connected to GND