User manual

EEP and Emulation Header User’s Guide
DS50002243A-page 22  2014 Microchip Technology Inc.
2.8 STOPWATCH CYCLE COUNTER
The Stopwatch (32-bit Instruction) Cycle Counter has the ability to perform the existing
basic instruction cycle counting (all instruction cycles counted) that exists on standard
Enhanced Midrange parts.
The stopwatch is available under Window>Debugging>Stopwatch
.
2.9 EXECUTION OUT-OF-BOUNDS DETECTION
An emulation header can be used to detect out-of-bounds execution of code.
Out-of-bounds code execution is detected by an event breakpoint that watches for PC
values that exceed the available program memory of the emulated MCU. The
out-of-bounds code execution condition is typically caused by a computed GOTO or
CALL that erroneously computes the index, or by loading PCLATH with an incorrect
value. Once code is halted due to the execution out-of-bounds event breakpoint the
‘Previous PC’ functionality can be used to identify the offending instruction.
The Out-of-bounds break option may be found and set up on the New Breakpoint
Dialog (Debug>New Breakpoint
) by choosing “Event” as the “Breakpoint Type” and
checking “Break on execution out of bounds”. After the breakpoint is created, it may be
edited by right clicking and selecting “Customize”.
See also, Section 2.5 “Enhanced Event Breakpoints”.
2.10 INTERRUPT CONTEXT DETECTION
An address or data breakpoint can be set based on the context of an interrupt. You can
set up the breakpoint so it only breaks when it is in the interrupt section of code (ISR),
only when it is in main line code, or when it is in either ISR or main code. This can assist
when attempting to narrow down issues in code regions.
Address/Data Breakpoints may be found and set up on the New Breakpoint Dialog
(Debug>New Breakpoint
) by choosing either “Address” or “Data” as the “Breakpoint
Type”. After the breakpoint is created, it may be edited by right clicking and selecting
“Customize”.
See also, Section 2.4 “Hardware Address/Data Breakpoints”.
Note: The count units are in instruction cycles, not in instructions (as not all
instructions execute in a single cycle).