Datasheet

Emulator User’s Guide for MPLAB X IDE
DS52085A-page 36  2013 Microchip Technology Inc.
3.6.3 I/O Port Trace Connections
Parallel trace is possible using a device 8-pin I/O port and the emulator logic probes.
This provides greater trace speed and data quantity, but limits emulator-to-target dis-
tance by the length of the logic probes. Figure 3-11 shows these additional
connections.
FIGURE 3-11: PARALLEL TRACE CONNECTIONS
For this trace configuration, seven (7) lines of data and one (1) line for clock are trans-
mitted. PORTx must be a port with 8 pins that has all 8 pins available for trace. The port
does not have to be one physical port but can be made up of pins from more than one
one port (see Project>Build Options>Project
, Trace tab, “I/O Port” drop-down box, for
allowable PORTx configurations). The port pins must not be multiplexed with the
currently-used PGC and PGM pins.
A basic configuration is shown in the following table.
As in Section 3.5.4 “Circuits That Will Prevent the Emulator From Functioning”,
do not use pull-up or pull-down resistors, capacitors or diodes on port pins, except as
specified.
For more on this type of trace, see Section 6.3.3.3 “I/O Port Trace”.
TABLE 3-4: I/O PORT TRACE CONNECTION EXAMPLE
PORTx pin Logic Probe pin
(1)
Content
0 EXT0 Data
1 EXT1 Data
2 EXT2 Data
3 EXT3 Data
4 EXT4 Data
5 EXT5 Data
6 EXT6 Data
7 EXT7
(2)
Clock
Note 1: For pin descriptions, see Section 12.4.4 “Logic Probe/External Trigger
Interface”.
2: Use a 10K pull-down resistor for noise reduction.
Application
PC Board
5
Device
PORTx
Logic
Probes
6:0
7
10K
ACTIVE STATUS
RESETFUNCTION
Emulator Pod
7
(Use EXT0:7)