Datasheet

 2006-2014 Microchip Technology Inc. DS70000178D-page 281
dsPIC30F1010/202X
Timing Characteristics
A/D Conversion
10-Bit High-speed (CHPS = 01, SIMSAM = 0,
ASAM = 0, SSRC = 000) .......................... 264
Band Gap Start-up Time........................................... 248
CLKO and I/O ........................................................... 245
External Clock........................................................... 240
I
2
C Bus Data
Master Mode.....................................................259
Slave Mode.......................................................261
I
2
C Bus Start/Stop Bits
Master Mode.....................................................259
Slave Mode.......................................................261
Input Capture (CAPX)...............................................251
Motor Control PWM Module...................................... 253
Motor Control PWM Module Fault............................. 253
OC/PWM Module...................................................... 252
Oscillator Start-up Timer........................................... 246
Output Compare Module........................................... 251
Power-up Timer ........................................................246
Reset.........................................................................246
SPI Module
Master Mode (CKE = 0)....................................254
Master Mode (CKE = 1)....................................255
Slave Mode (CKE = 0)...................................... 256
Slave Mode (CKE = 1)...................................... 257
Type A, B and C Timer External Clock ..................... 249
Watchdog Timer........................................................ 246
Timing Diagrams
PWM Output ............................................................. 104
Time-out Sequence on Power-up
(MCLR
Not Tied to VDD), Case 1......................211
Time-out Sequence on Power-up
(MCLR
Not Tied to VDD), Case 2......................212
Time-out Sequence on Power-up
(MCLR
Tied to VDD).......................................... 211
Timing Diagrams and Specifications
DC Characteristics - Internal RC Accuracy...............242
Timing Diagrams.See Timing Characteristics.
Timing Requirements
Band Gap Start-up Time........................................... 248
Brown-out Reset ....................................................... 247
CLKO and I/O ........................................................... 245
External Clock........................................................... 241
I
2
C Bus Data (Master Mode)..................................... 260
I
2
C Bus Data (Slave Mode).......................................262
Input Capture ............................................................ 251
Motor Control PWM Module...................................... 253
Oscillator Start-up Timer........................................... 247
Output Compare Module........................................... 251
Power-up Timer ........................................................247
Reset.........................................................................247
Simple OC/PWM Mode............................................. 252
SPI Module
Master Mode (CKE = 0)....................................254
Master Mode (CKE = 1)....................................255
Slave Mode (CKE = 0)...................................... 256
Slave Mode (CKE = 1)...................................... 258
Type A Timer External Clock ....................................249
Type B Timer External Clock ....................................250
Type C Timer External Clock....................................250
Watchdog Timer........................................................ 247
Timing Specifications
PLL Clock ................................................................. 242
Traps
Trap Sources.............................................................. 49
U
UART
Baud Rate Generator (BRG) .................................... 162
Enabling and Setting Up UART................................ 162
IrDA
Built-in Encoder and Decoder........................... 163
Receiving
8-bit or 9-bit Data Mode.................................... 163
Transmitting
8-bit Data Mode................................................ 163
9-bit Data Mode................................................ 163
Break and Sync Sequence............................... 163
UART1 Mode Register (U1MODE)................................... 164
UART1 Register Map........................................................ 168
UART1 Status and Control Register (U1STA).................. 166
Unit ID Locations .............................................................. 197
Universal Asynchronous Receiver Transmitter. See UART.
W
Wake-up from Sleep......................................................... 197
Wake-up from Sleep and Idle ............................................. 51
Watchdog Timer
Timing Characteristics .............................................. 246
Timing Requirements ............................................... 247
Watchdog Timer (WDT)............................................ 197, 214
Enabling and Disabling............................................. 214
Operation.................................................................. 214
WWW Address ................................................................. 273
WWW, On-Line Support ....................................................... 8