Datasheet

dsPIC30F1010/202X
DS70000178D-page 278  2006-2014 Microchip Technology Inc.
External Clock Input..........................................................207
External Clock Timing Characteristics
Type A, B and C Timer ............................................. 249
External Clock Timing Requirements................................241
Type A Timer ............................................................249
Type B Timer ............................................................250
Type C Timer ............................................................250
External Interrupt Requests ................................................51
F
Fast Context Saving............................................................51
Firmware Instructions........................................................219
Flash Program Memory.......................................................81
In-Circuit Serial Programming (ICSP).........................81
Run-Time Self-Programming (RTSP) .........................81
Table Instruction Operation Summary ........................81
I
I/O Pin Specifications
Input..........................................................................239
Output .......................................................................239
I/O Ports ..............................................................................77
Parallel I/O (PIO).........................................................77
I
2
C.....................................................................................153
I
2
C 10-bit Slave Mode Operation ......................................155
Reception..................................................................155
Transmission.............................................................155
I
2
C 7-bit Slave Mode Operation ........................................155
Reception..................................................................155
Transmission.............................................................155
I
2
C Master Mode
Baud Rate Generator................................................158
Clock Arbitration........................................................158
Multi-Master Communication, Bus Collision
and Bus Arbitration ...........................................158
Reception..................................................................157
Transmission.............................................................157
I
2
C Module
Addresses.................................................................155
Bus Data Timing Characteristics
Master Mode.....................................................259
Slave Mode.......................................................261
Bus Data Timing Requirements
Master Mode.....................................................260
Slave Mode.......................................................262
Bus Start/Stop Bits Timing Characteristics
Master Mode.....................................................259
Slave Mode.......................................................261
General Call Address Support .................................. 157
Interrupts...................................................................156
IPMI Support .............................................................157
Master Operation ......................................................157
Master Support .........................................................157
Operating Function Description ................................153
Operation During CPU Sleep and Idle Modes ..........158
Pin Configuration ......................................................153
Programmer’s Model.................................................153
Registers...................................................................153
Slope Control ............................................................157
Software Controlled Clock Stretching
(STREN = 1) .....................................................156
Various Modes ..........................................................153
I
2
C Register Map...............................................................159
Idle Current (I
IDLE)............................................................. 235
In-Circuit Debugger...........................................................217
In-Circuit Serial Programming (ICSP) ...............................197
Initialization Condition for RCON Register Case 1 ........... 213
Initialization Condition for RCON Register Case 2 ........... 213
Input Capture (CAPX) Timing Characteristics .................. 251
Input Capture Interrupts...................................................... 99
Input Capture Module ......................................................... 97
Simple Capture Event Mode....................................... 98
Sleep and Idle Modes................................................. 99
Input Capture Register Map.............................................. 100
Input Capture Timing Requirements................................. 251
Input Change Notification ................................................... 78
Input Change Notification Register Map............................. 80
Instruction Addressing Modes ............................................ 41
File Register Instructions............................................ 41
Fundamental Modes Supported ................................. 41
MAC Instructions ........................................................ 42
MCU Instructions ........................................................ 42
Move and Accumulator Instructions............................ 42
Other Instructions ....................................................... 42
Instruction Set................................................................... 219
Instruction Set Overview................................................... 222
Inter-Integrated Circuit. See I
2
C.
Internal Clock Timing Examples ....................................... 242
Internet Address ............................................................... 273
Interrupt Control and Status Register (INTTREG) .............. 74
Interrupt Control Register 1 (INTCON1) ............................. 52
Interrupt Control Register 2 (INTCON2) ............................. 54
Interrupt Controller Register Map ....................................... 75
Interrupt Enable Control Register 1 (IEC1)......................... 61
Interrupt Enable Control Register 2 (IEC2)......................... 62
Interrupt Flag Status Register 0 (IFS0)............................... 55
Interrupt Flag Status Register 1 (IFS1)............................... 57
Interrupt Flag Status Register 2 (IFS2)............................... 58
Interrupt Priority .................................................................. 48
Interrupt Priority Control Register 0 (IPC0)......................... 63
Interrupt Priority Control Register 1 (IPC1)......................... 64
Interrupt Priority Control Register 10 (IPC10)..................... 73
Interrupt Priority Control Register 2 (IPC2)......................... 65
Interrupt Priority Control Register 3 (IPC3)......................... 66
Interrupt Priority Control Register 4 (IPC4)......................... 67
Interrupt Priority Control Register 5 (IPC5)......................... 68
Interrupt Priority Control Register 6 (IPC6)......................... 69
Interrupt Priority Control Register 7 (IPC7)......................... 70
Interrupt Priority Control Register 8 (IPC8)......................... 71
Interrupt Priority Control Register 9 (IPC9)......................... 72
Interrupt Sequence ............................................................. 51
Interrupt Stack Frame................................................. 51
Interrupts............................................................................. 47
Traps .......................................................................... 49
L
Leading Edge Blanking Control Register (LEBCONx)...... 120
Linear Feedback Register (LFSR) .................................... 202
Load Conditions................................................................ 240
M
Memory Organization ......................................................... 29
Microchip Internet Web Site.............................................. 273
Modulo Addressing............................................................. 43
Applicability................................................................. 45
Operation Example..................................................... 44
Start and End Address ............................................... 43
W Address Register Selection.................................... 43
MPLAB Assembler, Linker, Librarian................................ 228
MPLAB ICD 3 In-Circuit Debugger ................................... 229
MPLAB PM3 Device Programmer .................................... 229
MPLAB REAL ICE In-Circuit Emulator System ................ 229