Datasheet

Current
Memory
Family
PAGE 73
SPI Compatible Serial EEPROM Family – Page Write mode, HOLD pin, software enabled block write protection and hardware write-protect pin. Supports SPI modes 0, 3.
(continued)
25LC160A 1M 16 Kbits (x8) 16B 5 ms 10 MHz 2.5 to 5.5 I, E P, SN, ST, MS
25AA160A 1M 16 Kbits (x8) 16B 5 ms 10 MHz 1.8 to 5.5 I P, SN, ST, MS
25LC160B 1M 16 Kbits (x8) 32B 5 ms 10 MHz 2.5 to 5.5 I, E P, SN, ST, MS
25AA160B 1M 16 Kbits (x8) 32B 5 ms 10 MHz 1.8 to 5.5 I P, SN, ST, MS
25C320 100K 32 Kbits (x8) 32B 5 ms 3 MHz 4.5 to 5.5 I, E P, S N
25LC320 1M 32 Kbits (x8) 32B 5 ms 2 MHz 2.5 to 5.5 I, E P, SN, X/ST
25AA320 1M 32 Kbits (x8) 32B 5 ms 1 MHz 1.8 to 5.5 I P, SN, X/ST
25LC640 1M 64 Kbits (x8) 32B 5 ms 3 MHz 2.5 to 5.5 I, E P, SN, X/ST
25AA640 1M 64 Kbits (x8) 32B 5 ms 1 MHz 1.8 to 5.5 I P, SN, X/ST
25LC256
1M 256 Kbits (x8) 64B 5 ms 10 MHz 2.5 to 5.5 I. E P, SN, ST, MF
25AA256
1M 256 Kbits (x8) 64B 5 ms 10 MHz 1.8 to 5.5 I P, SN, ST, MF
Product
E/W
Cycles
Density
(Organization)
Write Speed
Max. Clock
Frequency
Operating Voltage (V) Temps Unique Features
Packages
Identification Products (Application-specific products for monitors, DRAM modules, ACR risers and other plug-and-play applications)
24LC21A 1M 1 Kbit (x8) 10 ms 400 kHz 2.5 to 5.5 C, I
Completely implements DDC1™/DDC2™ interface for VESA
monitor identification. Improved noise filter. Write protection
pin plus “return to DDC1” feature.
P, S N
24LCS21A 1M 1 Kbit (x8) 10 ms 400 kHz 2.5 to 5.5 C, I
Same features as 24LC21A plus software enabled write-
protect pin.
P, S N
24LCS22A 1M 2 Kbits (x8) 10 ms 400 kHz 2.5 to 5.5 I
Implements VESA E-EDID 1.3 for flat panels and projectors.
Includes “return to DDC1” feature and software - enabled write
protect pin.
P, S N
24LC024 1M 2 Kbits (x8) 10 ms 400 kHz 2.5 to 5.5 C, I
Addressable, hardware write protection for DRAM DIMM
modules and other applications.
P, SN, ST, MS
24LC025 1M 2 Kbits (x8) 10 ms 400 kHz 2.5 to 5.5 C, I Addressable. No write-protect. P, SN, ST, MS
24AA52 1M 2 Kbits (x8) 10 ms 400 kHz 1.8 to 5.5 I
Addressable, hardware write protection and software write
protection for lower half of the array. Designed for DRAM
DIMM modules.
P, SN, ST, MS
24LCS52 1M 2 Kbits (x8) 10 ms 400 kHz 2.5 to 5.5 I P, SN, ST, MS
Product
E/W
Cycles
Density
(Organization)
Page Size Write Speed
Max. Clock
Frequency
Operating Voltage
(V)
Temps Unique Features
Packages
(1)
NOTE 1. X/ST package code denotes rotated pinout.