Datasheet
6
PICtail Plus (Parallel, J1)
The J1 board edge contacts are available for evaluating the ENC624J600 device’s Parallel
Interface modes. Due to the large number of pins required to support a parallel interface,
only the Explorer 16 and PIC32 I/O Expansion Boards are set up to use this feature. The
pinout of the J1 connector is set up to be driven by the host microcontroller via the Parallel
Master Port (PMP) peripheral available on select processors. In some cases, where the
PMP peripheral or necessary mode is unavailable, it is possible to bit-bang the parallel inter-
face at reduced performance. However, in other cases where not all of the necessary pins
are connected, it is infeasible to use the J1 parallel interface and use of the J2 SPI
connector is required instead.
Even when a host processor has all of the necessary pins, there are various limitations due
to pin multiplexing performed on the host motherboard. At the time of the Fast 100 Mbps
Ethernet PICtail Plus product development, there are several known issues:
• On the Explorer 16, it is not possible to use the LCD module with the ENC624J600 in
Parallel mode. The LCD interfaces to the same PMP lines as required for the
ENC624J600; however, unlike the ENC624J600, the LCD does not include a chip select
line. Therefore, it remains listening on the parallel bus at all times and all communications
to/from the ENC624J600 also get processed by the LCD controller.
• On the Explorer 16, PSP Modes 2, 4, 6 and 10 must not be used. For these interface
modes, any read operation from the ENC624J600 will simultaneously cause a read from
the LCD, causing bus contention. To avoid this, the RD5/PMPRD signal on the
Explorer 16 must be disconnected from the LCD. The LCD R/W
input should then be tied
to V
SS to force it into Write mode at all times.
• On the Explorer 16, PSP Modes 3 and 4 should not be used. For these 16-Bit
Demultiplexed modes, the Explorer 16 board’s U5 25LC256 EEPROM may become
selected and cause bus contention or EEPROM data corruption while communicating
with the ENC624J600. The EEPROM must be removed from the board to avoid this
potential problem.
• On the Explorer 16, the RF4/PMPA9/U2RX and RF5/PMPA8/U2TX pins have UART2
peripheral features multiplexed onto the same pins, as required for the PMP Address 9
and 8 control lines. Therefore, in PSP Modes 1-6, with full direct addressing capability, the
Explorer 16 board’s RS-232 COM port (P1) cannot be used. However, with indirect
addressing, the UART is still available.
• On the Explorer 16, the D8 LED cannot be used. The RA5/TDO control signal connected
to D8 is used as the chip select control signal to the ENC624J600.
• On the Explorer 16, when using PSP Modes 3, 4, 9 or 10 (all 16-bit modes), the S4, S3
and S6 push buttons cannot be used while communicating with the ENC624J600. The I/O
pins used for these buttons are required for PMD13, PMD14 and PMD15, respectively.
• On the PIC32 Starter Kit (Rev C) and PIC32 USB Starter Board (Rev B) for the PIC32 I/O
Expansion Board, the S1, S2 and S3 push buttons short the PMPD14, PMPD15 and
PMPD13 signals to GND. As a result, when the processor is communicating to the
ENC624J600 using PSP Modes 3, 4, 9 or 10 (all 16-bit modes), these push buttons can-
not be used. Also, since the buttons short the pins directly to GND without current limiting
resistors, users must not push any of the buttons during communications as this will
cause bus contention and corrupt communications with the ENC624J600.
Other compatibility restrictions may exist and may be created in the future for new PIMs and
PIC32 starter boards. Be sure to check the appropriate schematics of all involved
components to ensure compatibility.