Datasheet

93LC76/86
DS21131E-page 8 Preliminary  2004 Microchip Technology Inc.
FIGURE 3-1: SYNCHRONOUS DATA TIMING
FIGURE 3-2: READ
FIGURE 3-3: EWEN
The memory automatically cycles to the next register.
VIH
VIL
VIH
VIL
VIH
VOH
VOL
VOH
VOL
VIL
TSV
TDIS
TPD
TDIH
TCSS TCKH TCKL
TPD
TCSH
TCZ
TCZ
CS
CLK
DI
DO
DO
(Program)
(Read)
Status Valid
110A
N
A
0
D
N
D
N
D
0
D
0
...
...
...
High-impedance
TCSL
CS
CLK
DI
DO
0
CS
CLK
DI
11100
T
CSL
XX
...
ORG = V
CC, 8 X’s
ORG = VSS, 9 X’s