Datasheet

 2002-2012 Microchip Technology Inc. DS21712C-page 9
93LC46/56/66
FIGURE 2-5: WRAL TIMING
FIGURE 2-6: ERASE TIMING
FIGURE 2-7: ERAL TIMING
CS
CLK
DI
DO
High-Z
1
0
0
0
1 X
•••
X
Dx •••
D0
High-Z
Busy
Ready
14
Ensured by Characterization at VCC = 4.5V to +5.5V.
6
11
10
CS
CLK
DI
DO
6
Check Status
1
1
1 An
An-1 An-2
•••
A0
11 10
Busy
Ready
High-Z
12
High-Z
CS
CLK
DI
DO
6
Check Status
100 10X
•••
X
11 10
Busy
Ready
High-Z
13
High-Z
Ensured by Characterization at Vcc = 4.5V to +5.5V.