Datasheet

 1998-2012 Microchip Technology Inc. DS20067K-page 9
93AA46/56/66
FIGURE 2-5: WRITE TIMING
FIGURE 2-6: WRAL TIMING
FIGURE 2-7: ERASE TIMING
11
0
A
n
A0
CS
CLK
DI
DO
TCSL
D0
Dx
Tri-state
TWC
Busy
Ready
Ensured at Vcc = +4.5V to +6.0V.
1
X0
CS
CLK
DI
DO
TCSL
D0
Dx
Tri-state
TWL
Busy
Ready
Standby
0
0
X
Tri-state
1
An-11
CS
CLK
DI
TCSL
A0
An-2
Standby
1
DO
Tri-state
TWC
Busy
Ready
An
Check Status
Tri-state
TSV
TCZ