Datasheet

25LC512

DS22065C-page 16  2010 Microchip Technology Inc.

2.10 CHIP ERASE

The CHIP ERASE instruction will erase all bits (FFh) in

the array. A Write Enable (WREN) instruction must be

given prior to executing a CHIP ERASE. This is done

by setting CS

low and then clocking out the proper

instruction into the 25LC512. After all eight bits of the

instruction are transmitted, the CS must be brought

high to set the write enable latch.

The CHIP ERASE instruction is entered by driving the

low, followed by the instruction code (Figure 2-10)

onto the SI line.

The CS

pin must be driven high after the eighth bit of

the instruction code has been given or the CHIP

ERASE instruction will not be executed. Once the CS

pin is driven high the self-timed CHIP ERASE instruc-

tion begins. While the device is executing the CHIP

ERASE instruction the WIP bit in the STATUS register

can be read to determine when the CHIP ERASE

instruction is complete.

The CHIP ERASE instruction is ignored if either of the

Block Protect bits (BP0, BP1) are not 0, meaning ¼,

½, or all of the array is protected.

FIGURE 2-10: CHIP ERASE SEQUENCE

SCK

0 2345671

High-Impedance

111000 11