Datasheet

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25AA256/25LC256

Device Selection Table

Features:

• Max. Clock 10 MHz

• Low-Power CMOS Technology:

- Max. Write Current: 5 mA at 5.5V, 10 MHz

- Read Current: 6 mA at 5.5V, 10 MHz

- Standby Current: 1 μA at 5.5V

• 32,768 x 8-bit Organization

• 64-Byte Page

• Self-Timed Erase and Write Cycles (5 ms max.)

• Block Write Protection:

- Protect none, 1/4, 1/2 or all of array

• Built-In Write Protection:

- Power-on/off data protection circuitry

- Write enable latch

- Write-protect pin

• Sequential Read

• High Reliability:

- Endurance: 1,000,000 erase/write cycles

- Data retention: > 200 years

- ESD protection: > 4000V

• Temperature Ranges Supported:

• Pb-Free and RoHS Compliant

Pin Function Table

Description:

The Microchip Technology Inc. 25AA256/25LC256

(25XX256

) are 256 Kbit Serial Electrically Erasable

PROMs. The memory is accessed via a simple Serial

Peripheral Interface (SPI) compatible serial bus. The

bus signals required are a clock input (SCK) plus sep-

arate data in (SI) and data out (SO) lines. Access to the

device is controlled through a Chip Select (CS

) input.

Communication to the device can be paused via the

hold pin (HOLD). While the device is paused,

transitions on its inputs will be ignored, with the

exception of Chip Select, allowing the host to service

higher priority interrupts.

The 25XX256 is available in standard packages

including 8-lead PDIP and SOIC, and advanced

packaging including 8-lead DFN and 8-lead TSSOP.

Package Types (not to scale)

Part Number VCC Range Page Size Temp. Ranges Packages

25LC256 2.5-5.5V 64 Byte I, E P, SN, SM, ST, MF

25AA256 1.8-5.5V 64 Byte I P, SN, SM, ST, MF

- Industrial (I): -40°Cto +85°C

- Automotive (E): -40°C to +125°C

Name Function

CS Chip Select Input

SO Serial Data Output

Write-Protect

VSS Ground

SI Serial Data Input

SCK Serial Clock Input

HOLD

Hold Input

VCC Supply Voltage

HOLD

SCK

PDIP/SOIC

(P, SN, SM)

TSSOP

(ST)

DFN

VSS

HOLD

SCK

VCC

(MF)

HOLD

SCK

Rotated TSSOP

(ST)

HOLD

SCK

256K SPI Bus Serial EEPROM

* 25XX256 is used in this document as a generic part number for the 25AA256, 25LC256 devices.

Summary of content (26 pages)

PAGE 1
25AA256/25LC256 256K SPI Bus Serial EEPROM Device Selection Table Part Number VCC Range Page Size Temp. Ranges Packages 25LC256 2.5-5.5V 64 Byte I, E P, SN, SM, ST, MF 25AA256 1.8-5.5V 64 Byte I P, SN, SM, ST, MF Features: Description: • Max. Clock 10 MHz • Low-Power CMOS Technology: - Max. Write Current: 5 mA at 5.5V, 10 MHz - Read Current: 6 mA at 5.5V, 10 MHz - Standby Current: 1 μA at 5.5V • 32,768 x 8-bit Organization • 64-Byte Page • Self-Timed Erase and Write Cycles (5 ms max.
PAGE 2
5AA256/25LC256 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (†) VCC .............................................................................................................................................................................6.5V All inputs and outputs w.r.t. VSS ......................................................................................................... -0.6V to VCC +1.0V Storage temperature .........................................................................
PAGE 3
25AA256/25LC256 TABLE 1-2: AC CHARACTERISTICS AC CHARACTERISTICS Param. Sym. No. Characteristic Industrial (I): TA = -40°C to +85°C Automotive (E): TA = -40°C to +125°C VCC = 1.8V to 5.5V VCC = 2.5V to 5.5V Min. Max. Units Test Conditions — — — 10 5 3 MHz MHz MHz 4.5V ≤ Vcc ≤ 5.5V 2.5V ≤ Vcc < 4.5V 1.8V ≤ Vcc < 2.5V 1 FCLK Clock Frequency 2 TCSS CS Setup Time 50 100 150 — — — ns ns ns 4.5V ≤ Vcc ≤ 5.5V 2.5V ≤ Vcc < 4.5V 1.8V ≤ Vcc < 2.
PAGE 4
25AA256/25LC256 TABLE 1-2: AC CHARACTERISTICS (CONTINUED) Industrial (I): TA = -40°C to +85°C Automotive (E): TA = -40°C to +125°C AC CHARACTERISTICS Param. Sym. No. Characteristic Min. Max. Units VCC = 1.8V to 5.5V VCC = 2.5V to 5.5V Test Conditions 18 THZ HOLD Low to Output High-Z 30 60 160 — — — ns ns ns 4.5V ≤ Vcc ≤ 5.5V (Note 1) 2.5V ≤ Vcc < 4.5V (Note 1) 1.8V ≤ Vcc < 2.5V (Note 1) 19 THV HOLD High to Output Valid 30 60 160 — — — ns ns ns 4.5V ≤ Vcc ≤ 5.5V 2.5V ≤ Vcc < 4.5V 1.
PAGE 5
25AA256/25LC256 FIGURE 1-1: HOLD TIMING CS 17 16 17 16 SCK 18 SO n+2 SI n+2 n+1 n 19 High-Impedance n 5 Don’t Care n+1 n-1 n n n-1 HOLD FIGURE 1-2: SERIAL INPUT TIMING 4 CS 2 7 Mode 1,1 SCK 8 3 12 11 Mode 0,0 5 SI 6 MSB in LSB in High-Impedance SO FIGURE 1-3: SERIAL OUTPUT TIMING CS 9 3 10 Mode 1,1 SCK Mode 0,0 13 SO 14 MSB out SI © 2007 Microchip Technology Inc.
PAGE 6
25AA256/25LC256 2.0 FUNCTIONAL DESCRIPTION 2.1 Principles of Operation The 25XX256 is a 32,768-byte Serial EEPROM designed to interface directly with the Serial Peripheral Interface (SPI) port of many of today’s popular microcontroller families, including Microchip’s PIC® microcontrollers. It may also interface with microcontrollers that do not have a built-in SPI port by using discrete I/O lines programmed properly in firmware to match the SPI protocol.
PAGE 7
25AA256/25LC256 BLOCK DIAGRAM STATUS Register HV Generator Memory Control Logic I/O Control Logic EEPROM Array X Dec Page Latches SI SO Y Decoder CS SCK Sense Amp.
PAGE 8
25AA256/25LC256 FIGURE 2-2: BYTE WRITE SEQUENCE CS Twc 0 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31 SCK Instruction SI 0 0 0 0 0 16-bit Address 0 2 0 15 14 13 12 1 Data Byte 1 0 7 6 5 4 3 2 1 0 High-Impedance SO FIGURE 2-3: PAGE WRITE SEQUENCE CS 0 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31 SCK Instruction SI 0 0 0 0 0 16-bit Address 0 1 Data Byte 1 2 0 15 14 13 12 1 0 7 6 5 4 3 2 1 0 CS 32 33 34 35 36 37 38 39 40
PAGE 9
25AA256/25LC256 2.4 Write Enable (WREN) and Write Disable (WRDI) The following is a list of conditions under which the write enable latch will be reset: • • • • The 25XX256 contains a write enable latch. See Table 2-1 for the Write-Protect Functionality Matrix. This latch must be set before any write operation will be completed internally. The WREN instruction will set the latch, and the WRDI will reset the latch.
PAGE 10
25AA256/25LC256 2.5 Read Status Register Instruction (RDSR) The Write Enable Latch (WEL) bit indicates the status of the write enable latch and is read-only. When set to a ‘1’, the latch allows writes to the array, when set to a ‘0’, the latch prohibits writes to the array. The state of this bit can always be updated via the WREN or WRDI commands, regardless of the state of write protection on the STATUS register. These commands are shown in Figure 2-4 and Figure 2-5.
PAGE 11
25AA256/25LC256 2.6 Write Status Register Instruction (WRSR) See Figure 2-7 for the WRSR timing sequence. TABLE 2-3: The Write Status Register instruction (WRSR) allows the user to write to the nonvolatile bits in the STATUS register as shown in Table 2-2. The user is able to select one of four levels of protection for the array by writing to the appropriate bits in the STATUS register. The array is divided up into four segments.
PAGE 12
25AA256/25LC256 2.7 Data Protection 2.
PAGE 13
25AA256/25LC256 3.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 3-1. TABLE 3-1: Name PIN FUNCTION TABLE PDIP/SOIC Rotated TSSOP/DFN TSSOP Function The WP pin function is blocked when the WPEN bit in the STATUS register is low. This allows the user to install the 25XX256 in a system with WP pin grounded and still be able to write to the STATUS register. The WP pin functions will be enabled when the WPEN bit is set high. 3.
PAGE 14
25AA256/25LC256 4.0 PACKAGING INFORMATION 4.1 Package Marking Information Example: 8-Lead DFN XXXXXXX T/XXXXX YYWW NNN 25LC256 I/MF e3 0528 1L7 8-Lead PDIP Example: XXXXXXXX T/XXXNNN YYWW 25LC256 I/P e3 1L7 0528 8-Lead SOIC (3.90 mm) Example: 25LC256I SN e3 0528 1L7 XXXXXXXT XXXXYYWW NNN 8-Lead TSSOP Example: 5LE I528 1L7 XXXX TYWW NNN Legend: XX...
PAGE 15
25AA256/25LC256 8-Lead Plastic Dual Flat, No Lead Package (MF) – 6x5 mm Body [DFN-S] PUNCH SINGULATED Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D D1 e b N L N K E E2 E1 EXPOSED PAD NOTE 1 2 2 1 1 NOTE 1 D2 TOP VIEW BOTTOM VIEW φ A2 A A1 A3 NOTE 2 Units Dimension Limits Number of Pins MILLIMETERS MIN N NOM MAX 8 Pitch e Overall Height A – 0.85 Molded Package Thickness A2 – 0.
PAGE 16
25AA256/25LC256 8-Lead Plastic Dual In-Line (P) – 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N NOTE 1 E1 1 3 2 D E A2 A L A1 c e eB b1 b Units Dimension Limits Number of Pins INCHES MIN N NOM MAX 8 Pitch e Top to Seating Plane A – – .210 Molded Package Thickness A2 .115 .130 .195 Base to Seating Plane A1 .015 – – Shoulder to Shoulder Width E .290 .310 .
PAGE 17
25AA256/25LC256 8-Lead Plastic Small Outline (SN) – Narrow, 3.90 mm Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D e N E E1 NOTE 1 1 2 3 α h b h A2 A c φ L A1 L1 Units Dimension Limits Number of Pins β MILLIMETERS MIN N NOM MAX 8 Pitch e Overall Height A – 1.27 BSC – Molded Package Thickness A2 1.25 – – Standoff § A1 0.10 – 0.
PAGE 18
25AA256/25LC256 (JEITA/EIAJ Standard, Formerly called SOIC) 8-Lead Plastic Small Outline (SM) – Medium, 5.28 mm Body [SOIJ] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D N E E1 1 2 e b α A2 A c φ β A1 Units Dimension Limits Number of Pins L MILLIMETERS MIN N NOM MAX 8 Pitch e Overall Height A 1.77 1.27 BSC – Molded Package Thickness A2 1.75 – 1.98 Standoff § A1 0.05 – 0.
PAGE 19
25AA256/25LC256 8-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm Body [TSSOP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D N E E1 NOTE 1 1 2 b e c A φ A2 A1 L L1 Units Dimension Limits Number of Pins MILLIMETERS MIN N NOM MAX 8 Pitch e Overall Height A – 0.65 BSC – Molded Package Thickness A2 0.80 1.00 1.05 Standoff A1 0.05 – 0.15 1.
PAGE 20
25AA256/25LC256 APPENDIX A: REVISION HISTORY Revision C (11/03) Corrections to Section 1.0, Electrical Characteristics. Revision D (06/05) Update package information Revision E (08/05) Remove Preliminary status. Revise Table 1-1, Params. D011 and D012. Revision F (05/07) Update Pb-free; Replace Package Drawings (Rev. AP); Update Product ID section. DS21822F-page 20 © 2007 Microchip Technology Inc.
PAGE 21
25AA256/25LC256 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
PAGE 22
25AA256/25LC256 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document.
PAGE 23
25AA256/25LC256 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X Device Tape & Reel – X /XX Temp Range Package Examples: a) b) Device: 25AA256 25LC256 25AA256X 25LC256X 256k-bit, 1.8V, 64-Byte Page, SPI Serial EEPROM 256k-bit, 2.5V, 64-Byte Page, SPI Serial EEPROM 256k-bit, 1.8V, 64-Byte Page, SPI Serial EEPROM, rotated pinout (ST only) 256k-bit, 2.
PAGE 25
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PAGE 26
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