Datasheet

 2003-2011 Microchip Technology Inc. DS21831E-page 3
25AA128/25LC128
TABLE 1-2: AC CHARACTERISTICS
AC CHARACTERISTICS
Industrial (I): TA = -40°C to +85°C VCC = 1.8V to 5.5V
Automotive (E): T
A = -40°C to +125°C VCC = 2.5V to 5.5V
Param.
No.
Sym. Characteristic Min. Max. Units Test Conditions
1F
CLK Clock Frequency —
—
—
10
5
3
MHz
MHz
MHz
4.5V Vcc  5.5V
2.5V Vcc  4.5V
1.8V Vcc  2.5V
2T
CSS CS Setup Time 50
100
150
—
—
—
ns
ns
ns
4.5V Vcc  5.5V
2.5V Vcc  4.5V
1.8V Vcc  2.5V
3T
CSH CS Hold Time 100
200
250
—
—
—
ns
ns
ns
4.5V Vcc  5.5V
2.5V Vcc  4.5V
1.8V Vcc  2.5V
4T
CSD CS Disable Time 50 — ns —
5 Tsu Data Setup Time 10
20
30
—
—
—
ns
ns
ns
4.5V Vcc  5.5V
2.5V Vcc  4.5V
1.8V Vcc  2.5V
6THD Data Hold Time 20
40
50
—
—
—
ns
ns
ns
4.5V Vcc  5.5V
2.5V Vcc  4.5V
1.8V Vcc  2.5V
7T
R CLK Rise Time — 100 ns (Note 1)
8T
F CLK Fall Time — 100 ns (Note 1)
9T
HI Clock High Time 50
100
150
—
—
—
ns
ns
ns
4.5V Vcc  5.5V
2.5V Vcc  4.5V
1.8V Vcc  2.5V
10 T
LO Clock Low Time 50
100
150
—
—
—
ns
ns
ns
4.5V Vcc  5.5V
2.5V Vcc  4.5V
1.8V Vcc  2.5V
11 T
CLD Clock Delay Time 50 — ns —
12 T
CLE Clock Enable Time 50 — ns —
13 T
V Output Valid from Clock
Low
—
—
—
50
100
160
ns
ns
ns
4.5V Vcc  5.5V
2.5V Vcc  4.5V
1.8V Vcc  2.5V
14 T
HO Output Hold Time 0 — ns (Note 1)
15 T
DIS Output Disable Time —
—
—
40
80
160
ns
ns
ns
4.5V Vcc  5.5V(Note 1)
2.5V Vcc  4.5V(Note 1)
1.8V Vcc  2.5V(Note 1)
16 T
HS HOLD Setup Time 20
40
80
—
—
—
ns
ns
ns
4.5V Vcc  5.5V
2.5V Vcc  4.5V
1.8V Vcc  2.5V
Note 1: This parameter is periodically sampled and not 100% tested.
2: TWC begins on the rising edge of CS after a valid write sequence and ends when the internal write cycle is
complete.
3: This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site:
www.microchip.com.