Datasheet

25AA320/25LC320/25C320
DS21227F-page 12 © 2008 Microchip Technology Inc.
3.7 Data Protection
The following protection has been implemented to
prevent inadvertent writes to the array:
• The write enable latch is reset on power-up
•A WRITE ENABLE instruction must be issued to
set the write enable latch
• After a byte write, page write or STATUS register
write, the write enable latch is reset
•CS
must be set high after the proper number of
clock cycles to start an internal write cycle
• Access to the array during an internal write cycle
is ignored and programming is continued
3.8 Power-On State
The 25XX320 powers on in the following state:
• The device is in low-power Standby mode
(CS
= 1)
• The write enable latch is reset
• SO is in high-impedance state
• A low level on CS
is required to enter active state
.
TABLE 3-3: WRITE-PROTECT FUNCTIONALITY MATRIX
WPEN WP WEL Protected Blocks Unprotected Blocks STATUS Register
xx0
Protected Protected Protected
0x1
Protected Writable Writable
1
Low
1
Protected Writable Protected
x
High
1
Protected Writable Writable