Datasheet

25AA640/25LC640

3.6 Write Status Register Instruction

(WRSR)

The Write Status Register instruction (WRSR) allows the

user to select one of four levels of protection for the

array by writing to the appropriate bits in the STATUS

The user has the ability to write-protect none, one, two,

or all four of the segments of the array. The partitioning

is controlled as shown in Table 3-2.

The Write-Protect Enable (WPEN) bit is a nonvolatile

bit that is available as an enable bit for the WP

pin. The

Write-Protect (WP

) pin and the Write-Protect Enable

(WPEN) bit in the STATUS register control the pro-

grammable hardware write-protect feature. Hardware

write protection is enabled when the WP

pin is low and

the WPEN bit is high. Hardware write protection is dis-

abled when either the WP pin is high or the WPEN bit

is low. When the chip is hardware write-protected, only

writes to nonvolatile bits in the STATUS register are dis-

abled. See Table 3-3 for a matrix of functionality on the

WPEN bit.

See Figure 3-7 for WRSR timing sequence.

TABLE 3-2: ARRAY PROTECTION

FIGURE 3-7: WRITE STATUS REGISTER TIMING SEQUENCE

BP1 BP0

Array Addresses

Write-Protected

00 none

01 upper 1/4

(1800h-1FFFh)

10 upper 1/2

(1000h-1FFFh)

11 all

(0000h-1FFFh)

91011 12131415

0 1000000

7654

210

Instruction Data to STATUS Register

High-Impedance

SCK

0 2345671