Datasheet

25AA320/25LC320/25C320

3.5 Read Status Register Instruction

(RDSR)

The Read Status Register instruction (RDSR) provides

access to the STATUS register. The STATUS register

may be read at any time, even during a write cycle. The

STATUS register is formatted as follows:

The Write-In-Process (WIP) bit indicates whether the

25XX320 is busy with a write operation. When set to a

‘

1’, a write is in progress; when set to a ‘0’, no write is

in progress. This bit is read-only.

The Write Enable Latch (WEL) bit indicates the status

of the write enable latch. When set to a ‘

1’, the latch

allows writes to the array, when set to a ‘

0’, the latch

prohibits writes to the array. The state of this bit can

always be updated via the WREN or WRDI commands

regardless of the state of write protection on the STA-

TUS register. This bit is read-only.

The Block Protection (BP0 and BP1) bits indicate

which blocks are currently write-protected. These bits

are set by the user issuing the WRSR instruction. These

bits are nonvolatile.

See Figure 3-6 for the RDSR timing sequence.

FIGURE 3-6: READ STATUS REGISTER TIMING SEQUENCE

76543 2 1 0

WPEN X X X BP1 BP0 WEL WIP

9101112131415

11000000

7654 210

Instruction

Data from STATUS Register

High-Impedance

SCK

0 2345671