Datasheet

 2003-2012 Microchip Technology Inc. DS21827H-page 7
25AA040A/25LC040A
BLOCK DIAGRAM
FIGURE 2-1: READ SEQUENCE
SI
SO
SCK
CS
HOLD
WP
STATUS
Register
I/O Control
Memory
Control
Logic
X
Dec
HV Generator
EEPROM
Array
Page Latches
Y Decoder
Sense Amp.
R/W Control
Logic
VCC
VSS
TABLE 2-1: INSTRUCTION SET
Instruction Name Instruction Format Description
READ
0000 A
8
011
Read data from memory array beginning at selected address
WRITE
0000 A
8
010
Write data to memory array beginning at selected address
WRDI
0000 x100
Reset the write enable latch (disable write operations)
WREN
0000 x110
Set the write enable latch (enable write operations)
RDSR
0000 x101
Read STATUS register
WRSR
0000 x001
Write STATUS register
Note: A
8
is the 9
th
address bit, which is used to address the entire 512 byte array.
x = don’t care.
SO
SI
SCK
CS
0 2345678910111
01A
8
00001A
7
A
6
A
5
A
4
A
1
A
0
76543210
Data Out
High-Impedance
A
3
A
2
Lower Address Byte
12
13 14
15 16
17
18
19
20
21 22 23
Instruction+Address MSb