Datasheet

 2003-2012 Microchip Technology Inc. DS21833G-page 11
25AA020A/25LC020A
2.6 Write Status Register Instruction
(WRSR)
The Write Status Register instruction (WRSR) allows
the user to write to the nonvolatile bits in the STATUS
register as shown in Tab l e 2- 2 . See Figure 2-7 for the
WRSR timing sequence. Four levels of protection for
the array are selectable by writing to the appropriate
bits in the STATUS register. The user has the ability to
write-protect none, one, two, or all four of the
segments of the array as shown in Table 2-3.
TABLE 2-3: ARRAY PROTECTION
FIGURE 2-7: WRITE STATUS REGISTER TIMING SEQUENCE (WRSR)
BP1 BP0
Array Addresses
Write-Protected
00
none
01
upper 1/4
(C0h-FFh)
10
upper 1/2
(80h-FFh)
11
all
(00h-FFh)
SO
SI
CS
9101112131415
01000000
7654
210
Instruction Data to STATUS register
High-Impedance
SCK
0 2345671
8
3
Note: An internal write cycle (TWC) is initiated on the rising edge of CS after a valid write STATUS register
sequence.