Datasheet

 2009 Microchip Technology Inc. DS21682E-page 3
24LCS22A
TABLE 1-2: AC CHARACTERISTICS
AC CHARACTERISTICS
Vcc = +2.5V to 5.5V
Industrial (I): T
A = -40°C to +85°C
Param.
No.
Sym Parameter Min Max Units Conditions
1F
CLK Clock frequency —
—
100
400
kHz 2.5V  VCC  5.5V
4.5V  V
CC  5.5V
2T
HIGH Clock high time 4000
600
—
—
ns 2.5V  VCC  5.5V
4.5V  V
CC  5.5V
3T
LOW Clock low time 4700
1300
—
—
ns 2.5V  VCC  5.5V
4.5V  V
CC  5.5V
4T
R SDA and SCL rise time —
—
1000
300
ns 2.5V  VCC  5.5V (Note 1)
4.5V V
CC  5.5V (Note 1)
5T
F SDA and SCL fall time —
—
300
300
ns (Note 1)
6T
HD:STA Start condition hold time 4000
600
—
—
ns 2.5V  VCC  5.5V
4.5V  V
CC  5.5V
7T
SU:STA Start condition setup time 4700
600
—
—
ns 2.5V  VCC  5.5V
4.5V  V
CC  5.5V
8T
HD:DAT Data input hold time 0
0
—
—
ns (Note 2)
9T
SU:DAT Data input setup time 250
100
—
—
ns 2.5V  VCC  5.5V
4.5V  V
CC  5.5V
10 T
SU:STO Stop condition setup time 4000
600
—
—
ns 2.5V  VCC  5.5V
4.5V  V
CC  5.5V
11 T
AA Output valid from clock
(Note 2)
—
—
3500
900
ns 2.5V  VCC  5.5V
4.5V  V
CC  5.5V
12 T
BUF Bus free time: Time the bus must be
free before a new transmission can
start
4700
1300
—
—
ns 2.5V  VCC  5.5V
4.5V  V
CC  5.5V
13 T
OF Output fall time from VIH
minimum to VIL maximum
—
20+0.1CB
250
250
ns 2.5V  VCC  5.5V (Note 1)
4.5V  V
CC  5.5V (Note 1)
14 T
SP Input filter spike suppression
(SDA and SCL pins)
—
—
50
50
ns (Notes 1 and 3)
15 T
WR Write cycle time (byte or page) —
—
10
10
ms
16 T
VAA Output valid from VCLK —
—
2000
1000
ns
17 T
VHIGH VCLK high time 4000
600
—
—
ns
18 T
VLOW VCLK low time 4700
1300
—
—
ns
19 T
VHST VCLK setup time 0
0
—
—
ns
20 T
SPVL VCLK hold time 4000
600
—
—
ns
21 T
VHZ Mode transition time —
—
1000
500
ns
22 T
VPU Transmit-only power-up time 0
0
—
—
ns
23 T
SPV Input filter spike suppression (VCLK
pin)
—
—
100
100
ns
24 — Endurance 1M — cycles 25°C, V
CC = 5.0V, Block mode
(Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the
falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: The combined T
SP and VHYS specifications are due to Schmitt Trigger inputs which provide improved noise spike suppression.
This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but established by characterization. For endurance estimates in a specific application, please consult
the Total Endurance™ Model which can be obtained from Microchip’s web site at www.microchip.com.