Datasheet

24LCS21A
DS21161H-page 8  2007 Microchip Technology Inc.
FIGURE 3-5: BUS TIMING START/STOP
FIGURE 3-6: BUS TIMING DATA
3.1.6 SLAVE ADDRESS
After generating a Start condition, the bus master
transmits the slave address consisting of a 7-bit device
code (1010000) for the 24LCS21A.
The eighth bit of slave address determines whether the
master device wants to read or write to the 24LCS21A
(Figure 3-7).
The 24LCS21A monitors the bus for its corresponding
slave address continuously. It generates an
Acknowledge bit if the slave address was true and it is
not in a programming mode.
FIGURE 3-7: CONTROL BYTE
ALLOCATION
SCL
SDA
Start Stop
VHYS
TSU:STO
THD:STA
TSU:STA
SCL
SDA
IN
SDA
OUT
T
SU:STA
TSP
TAA
TF
TLOW
THIGH
THD:STA
THD:DAT
TSU:DAT
TSU:STO
TBUF
TAA
TR
Operation Slave Address R/W
Read 1010000 1
Write 1010000 0
R/W A
1010000
Read/Write
Start
Slave Address