Datasheet

 2007 Microchip Technology Inc. DS21161H-page 13
24LCS21A
FIGURE 7-2: RANDOM READ
FIGURE 7-3: SEQUENTIAL READ
7.3 Sequential Read
Sequential reads are initiated in the same way as a
random read except that after the 24LCS21A transmits
the first data byte, the master issues an acknowledge
as opposed to a Stop condition in a random read. This
directs the 24LCS21A to transmit the next sequentially
addressed 8-bit word (Figure 7-3).
To provide sequential reads the 24LCS21A contains an
internal Address Pointer which is incremented by one
at the completion of each operation. This Address
Pointer allows the entire memory contents to be serially
read during one operation.
7.4 Noise Protection
The 24LCS21A employs a VCC threshold detector
circuit which disables the internal erase/write logic if the
VCC is below 1.5 volts at nominal conditions.
The SDA, SCL and VCLK inputs have Schmitt Trigger
and filter circuits which suppress noise spikes to assure
proper device operation even on a noisy bus.
Bus Activity
Master
SDA Line
Bus Activity
Control
Byte
Word
Address
Data n
A
C
K
S
T
A
R
T
N
O
S
T
A
R
Control
Byte
A
C
K
A
C
K
SS
T
P
S
T
O
P
10100000 00000111
A
C
K
A
C
K
P
Bus Activity
Master
SDA Line
Bus Activity
Control
Byte
Data n Data n+1
Data n+2 Data n+X
A
C
K
A
C
K
A
C
K
N
O
A
C
K
S
T
O
P