Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsIntegrated Circuits (ICs)SOIC 8 1 kBit 128 x 8

 2007 Microchip Technology Inc. DS21161H-page 1

24LCS21A

Features:

• Single Supply with Operation Down to 2.5V

• Completely Implements DDC1™/DDC2™ Inter-

face for Monitor Identification, Including Recovery

to DDC1

• Low-Power CMOS Technology:

- 1 mA active current, typical

-10 A standby current, typical at 5.5V

• 2-Wire Serial Interface Bus, I

C™ Compatible

• 100 kHz (2.5V) and 400 kHz (5V) Compatibility

• Self-Timed Write Cycle (including Auto-Erase)

• Hardware Write-Protect Pin

• Page Write Buffer for up to Eight Bytes

• 1,000,000 Erase/Write Cycles Ensured

• Data Retention > 200 years

• ESD Protection > 4000V

• 8-pin PDIP and SOIC Package

• Available for Extended Temperature Ranges:

- Industrial (I): -40°C to +70°C

• Pb-Free and RoHS Compliant

Description:

The Microchip Technology Inc. 24LCS21A is a

128 x 8-bit dual-mode Electrically Erasable PROM.

This device is designed for use in applications

requiring storage and serial transmission of configura-

tion and control information. Two modes of operation

have been implemented: Transmit-Only mode and

Bidirectional mode. Upon power-up, the device will be

in the Transmit-Only mode, sending a serial bit stream

of the memory array from 00h to 7Fh, clocked by the

VCLK pin. A valid high-to-low transition on the SCL

pin will cause the device to enter the Transition mode

and look for a valid control byte on the I

C bus. If it

detects a valid control byte from the master, it will

switch into Bidirectional mode, with byte selectable

read/write capability of the memory array using SCL.

If no control byte is received, the device will revert to

the Transmit-Only mode after it receives 128 consec-

utive VCLK pulses while the SCL pin is idle. The

24LCS21A also enables the user to write-protect the

entire memory array using its write-protect pin. The

24LCS21A is available in a standard 8-pin PDIP and

SOIC package in industrial temperature range.

Package Types

Block Diagram

Pin Function Table

Name Function

Write-Protect (active low)

SS Ground

SDA Serial Address/Data I/O

SCL Serial Clock (Bidirectional mode)

VCLK Serial Clock (Transmit-Only mode)

CC +2.5V to 5.5V Power Supply

NC No Connection

PDIP

SOIC

24LCS21A

Vss

Vcc

VCLK

SCL

SDA

24LCS21A

Vss

Vcc

VCLK

SCL

SDA

HV Generator

EEPROM

Array

Page Latches

YDEC

XDEC

Sense AMP

R/W

Control

Memory

Control

Logic

I/O

Control

Logic

SDA

SCL

VSS

VCLK

1K 2.5V Dual Mode I

™

Serial EEPROM

DDC is a trademark of the Video Electronics Standards Assoc.

C is a trademark of Philips Corporation.

Summary of content (20 pages)

PAGE 1
24LCS21A 1K 2.5V Dual Mode I2C™ Serial EEPROM PDIP 8 Vcc 7 VCLK 6 SCL 4 5 SDA NC 1 8 Vcc NC 2 7 VCLK WP 3 6 SCL Vss 4 5 SDA NC 1 NC 2 WP 3 Vss SOIC Block Diagram WP Description: The Microchip Technology Inc. 24LCS21A is a 128 x 8-bit dual-mode Electrically Erasable PROM. This device is designed for use in applications requiring storage and serial transmission of configuration and control information.
PAGE 2
4LCS21A 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings(†) VCC .............................................................................................................................................................................7.0V All inputs and outputs w.r.t. VSS ......................................................................................................... -0.6V to VCC +1.0V Storage temperature .................................................................................
PAGE 3
24LCS21A TABLE 1-2: AC CHARACTERISTICS Parameter Symbol Vcc = 2.5-4.5V Standard Mode Vcc = 4.5 - 5.
PAGE 4
24LCS21A 2.0 FUNCTIONAL DESCRIPTION it be initialized prior to valid data being sent in the Transmit-Only mode (Section 2.2 “Initialization Procedure”). In this mode, data is transmitted on the SDA pin in 8-bit bytes, with each byte followed by a ninth, null bit (Figure 2-1). The clock source for the TransmitOnly mode is provided on the VCLK pin, and a data bit is output on the rising edge on this pin. The eight bits in each byte are transmitted Most Significant bit first.
PAGE 5
24LCS21A 3.0 BIDIRECTIONAL MODE Once the device has switched into the Bidirectional mode, the VCLK input is disregarded, with the exception that a logic high level is required to enable write capability. This mode supports a two-wire Bidirectional data transmission protocol (I2C™). In this protocol, a device that sends data on the bus is defined to be the transmitter, and a device that receives data from the bus is defined to be the receiver.
PAGE 6
24LCS21A FIGURE 3-3: DISPLAY OPERATION PER DDC STANDARD PROPOSED BY VESA® The 24LCS21A was designed to comply to the portion of flowchart inside dash box. Display Power-on or DDC™ Circuit Powered from +5 volts Communication is idle Is Vsync present? No Yes High-to-Low transition on SCL? Send EDID™ continuously using Vsync as clock No Yes High-to-Low transition on SCL? No Yes Stop sending EDID. Switch to DDC2™ mode. Display has optional transition state ? DDC2 communication idle.
PAGE 7
24LCS21A 3.1 Bidirectional Mode Bus Characteristics The following bus protocol has been defined: • Data transfer may be initiated only when the bus is not busy. • During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high will be interpreted as a Start or Stop condition. Each data transfer is initiated with a Start condition and terminated with a Stop condition.
PAGE 8
24LCS21A FIGURE 3-5: BUS TIMING START/STOP SCL VHYS THD:STA TSU:STO TSU:STA SDA Start FIGURE 3-6: Stop BUS TIMING DATA TF TR THIGH TLOW SCL TSU:STA THD:STA SDA IN THD:DAT TSU:DAT TSU:STO TSP TBUF TAA TAA SDA OUT 3.1.6 SLAVE ADDRESS FIGURE 3-7: After generating a Start condition, the bus master transmits the slave address consisting of a 7-bit device code (1010000) for the 24LCS21A.
PAGE 9
24LCS21A 4.0 WRITE OPERATION 4.1 Byte Write Following the Start signal from the master, the slave address (four bits), three zero bits (000) and the R/W bit which is a logic low are placed onto the bus by the master transmitter. This indicates to the addressed slave receiver that a byte with a word address will follow after it has generated an Acknowledge bit during the ninth clock cycle.
PAGE 10
24LCS21A FIGURE 4-1: BYTE WRITE Bus Activity Master SDA Line S T A R T Word Address Control Byte S T O P Data S P A C K A C K Bus Activity A C K VCLK FIGURE 4-2: VCLK WRITE ENABLE TIMING SCL THD:STA SDA IN TSU:STO VCLK TVHST DS21161H-page 10 TSPVL © 2007 Microchip Technology Inc.
PAGE 11
24LCS21A 5.0 ACKNOWLEDGE POLLING FIGURE 5-1: Since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). Once the Stop condition for a Write command has been issued from the master, the device initiates the internally timed write cycle. ACK polling can be initiated immediately. This involves the master sending a Start condition followed by the control byte for a Write command (R/W = 0).
PAGE 12
24LCS21A 6.0 WRITE PROTECTION 7.0 When using the 24LCS21A in the Bidirectional mode, the VCLK pin can be used as a write-protect control pin. Setting VCLK high allows normal write operations, while setting VCLK low prevents writing to any location in the array. Connecting the VCLK pin to VSS would allow the 24LCS21A to operate as a serial ROM, although this configuration would prevent using the device in the Transmit-Only mode. Additionally, pin 3 performs a flexible write-protect function.
PAGE 13
24LCS21A FIGURE 7-2: RANDOM READ S T A R T Bus Activity Master Control Byte S T A R T Word Address S 1 0 1 0 0 0 0 0 SDA Line FIGURE 7-3: S T O P Data n S 1 0 1 0 0 0 0 1 A C K Bus Activity Control Byte A C K P A C K N O A C K SEQUENTIAL READ Bus Activity Master Data n Control Byte Data n+2 Data n+1 S T O P Data n+X P SDA Line Bus Activity 7.
PAGE 14
24LCS21A 8.0 PIN DESCRIPTIONS 8.1 SDA This pin is used to transfer addresses and data into and out of the device, when the device is in the Bidirectional mode. In the Transmit-Only mode, which only allows data to be read from the device, data is also transferred on the SDA pin. This pin is an open drain terminal, therefore the SDA bus requires a pull-up resistor to VCC (typical 10 KΩ for 100 kHz, 1 KΩ for 400 kHz).
PAGE 15
24LCS21A APPENDIX A: REVISION HISTORY Revision F Corrections to Section 1.0, Electrical Characteristics. Revision G Revised Section 8.4; Added On-Line Support page. Revision H Features Section - Add Pb-free and remove Commercial Temp; Revised Description; Table 1-1, Remove Commercial Temp, Revised Input/Output conditions; Revise Product ID section. © 2007 Microchip Technology Inc.
PAGE 16
24LCS21A PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX XXX Device Temperature Range Package Pattern Device: 24LCS21A Dual Mode I2C Serial EEPROM 24LCS21AT Dual Mode I2C Serial EEPROM (Tape and Reel) Temperature Range: I = -40°C to Package: P SN = = DS21161H-page 16 +85°C Plastic DIP (300 mil Body), 8-lead Plastic SOIC (150 mil Body), 8-lead © 2007 Microchip Technology Inc.
PAGE 17
24LCS21A THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
PAGE 18
24LCS21A READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document.
PAGE 19
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PAGE 20
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