Datasheet

© 2008 Microchip Technology Inc. DS21673G-page 3
24AA515/24LC515/24FC515
TABLE 1-2: AC CHARACTERISTICS
AC CHARACTERISTICS Industrial (I): VCC = +1.7V to 5.5V TA = -40°C to +85°C
Param.
No.
Sym. Characteristic Min. Max. Units Conditions
1F
CLK Clock frequency —
—
—
100
400
1000
kHz 1.7V ≤ VCC ≤ 2.5V
2.5V ≤ V
CC ≤ 5.5V
2.5V ≤ V
CC ≤ 5.5V (24FC515 only)
2T
HIGH Clock high time 4000
600
500
—
—
—
ns 1.7V ≤ VCC ≤ 2.5V
2.5V ≤ V
CC ≤ 5.5V
2.5V ≤ V
CC ≤ 5.5V (24FC515 only)
3T
LOW Clock low time 4700
1300
500
—
—
—
ns 1.7V ≤ VCC ≤ 2.5V
2.5V ≤ V
CC ≤ 5.5V
2.5V ≤ V
CC ≤ 5.5V (24FC515 only)
4T
R SDA and SCL rise time
(Note 1)
—
—
—
1000
300
300
ns 1.7V ≤ VCC ≤ 2.5V
2.5V ≤ V
CC ≤ 5.5V
2.5V ≤ V
CC ≤ 5.5V (24FC515 only)
5T
F SDA and SCL fall time
(Note 1)
—
—
300
100
ns All except, 24FC515
2.5V ≤ V
CC ≤ 5.5V (24FC515 only)
6T
HD:STA Start condition hold time 4000
600
250
—
—
—
ns 1.7V ≤ VCC ≤ 2.5V
2.5V ≤ V
CC ≤ 5.5V
2.5V ≤ V
CC ≤ 5.5V (24FC515 only)
7T
SU:STA Start condition setup time 4700
600
250
—
—
—
ns 1.7V ≤ VCC ≤ 2.5V
2.5V ≤ V
CC ≤ 5.5V
2.5V ≤ V
CC ≤ 5.5V (24FC515 only)
8T
HD:DAT Data input hold time 0 — ns (Note 2)
9T
SU:DAT Data input setup time 250
100
100
—
—
—
ns 1.7V ≤ VCC ≤ 2.5V
2.5V ≤ V
CC ≤ 5.5V
2.5V ≤ V
CC ≤ 5.5V (24FC515 only)
10 T
SU:STO Stop condition setup time 4000
600
250
—
—
—
ns 1.7V ≤ VCC ≤ 2.5V
2.5V ≤ V
CC ≤ 5.5V
2.5V ≤ V
CC ≤ 5.5V (24FC515 only)
11 T
SU:WP WP setup time 4000
600
600
—
—
—
ns 1.7V ≤ VCC ≤ 2.5V
2.5V ≤ V
CC ≤ 5.5V
2.5V ≤ V
CC ≤ 5.5V (24FC515 only)
12 T
HD:WP WP hold time 4700
1300
1300
—
—
—
ns 1.7V ≤ VCC ≤ 2.5V
2.5V ≤ V
CC ≤ 5.5V
2.5V ≤ V
CC ≤ 5.5V (24FC515 only)
13 T
AA Output valid from clock
(Note 2)
—
—
—
3500
900
400
ns 1.7V ≤ VCC ≤ 2.5V
2.5V ≤ V
CC ≤ 5.5V
2.5V ≤ V
CC ≤ 5.5V (24FC515 only)
14 T
BUF Bus free time: Time the bus
must be free before a new
transmission can start
4700
1300
500
—
—
—
ns 1.7V ≤ VCC ≤ 2.5V
2.5V ≤ V
CC ≤ 5.5V
2.5V ≤ V
CC ≤ 5.5V (24FC515 only)
15 T
OF Output fall time from VIH
minimum to VIL maximum
C
B ≤ 100 pF
10 + 0.1C
B 250
250
ns All except, 24FC515 (Note 1)
24FC515 (Note 1)
16 T
SP Input filter spike suppression
(SDA and SCL pins)
— 50 ns All except, 24FC515 (Notes 1 and 3)
17 T
WC Write cycle time (byte or page) — 5 ms
18 Endurance 1 M — cycles 25°C (Note 4)
Note 1: Not 100% tested. C
B = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum
300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: The combined T
SP and VHYS specifications are due to new Schmitt Trigger inputs which provide improved noise spike
suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but established by characterization. For endurance estimates in a specific application,
please consult the Total Endurance™ Model which can be obtained from Microchip’s web site at www.microchip.com.