Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsIntegrated Circuits (ICs)PDIP 8 512 kBit 64 K x 8

24AA515/24LC515/24FC515

Device Selection Table

Features:

• Single Supply with Operation Down to 1.7V for

24AAXX Devices, 2.5V for 24LCXX Devices

• Low-Power CMOS Technology:

- Active current 500 uA, typical

- Standby current 100 nA, typical

• 2-Wire Serial Interface, I

C™ Compatible

• Cascadable up to Four Devices

• Schmitt Trigger Inputs for Noise Suppression

• Output Slope Control to Eliminate Ground Bounce

• 100 kHz and 400 kHz Clock Compatibility

• Page Write Time 5 ms max.

• Self-Timed Erase/Write Cycle

• 64-Byte Page Write Buffer

• Hardware Write Protect

• ESD Protection >4000V

• More than 1 Million Erase/Write Cycles

• Data Retention >200 years

• Factory Programming Available

• Packages Include 8-lead PDIP, SOIJ

• Pb-Free and RoHS Compliant

• Temperature Ranges:

- Industrial (I): -40°C to +85°C

- Automotive (E):-40°C to +125°C

Description:

The Microchip Technology Inc. 24AA515/24LC515/

24FC515 (24XX515*) is a 64K x 8 (512K bit) Serial

Electrically Erasable PROM, capable of operation

across a broad voltage range (1.7V to 5.5V). It has

been developed for advanced, low-power applications

such as personal communications or data acquisition.

This device has both byte write and page write capabil-

ity of up to 64 bytes of data. This device is capable of

both random and sequential reads.

Reads may be sequential within address boundaries

0000h to 7FFFh and 8000h to FFFFh. Functional

address lines allow up to four devices on the same data

bus. This allows for up to 2 Mbits total system

EEPROM memory. This device is available in the

standard 8-pin plastic DIP and SOIJ packages.

Package Type

Block Diagram

Part

Number

VCC

Range

Max. Clock

Frequency

Temp.

Ranges

24AA515 1.8-5.5V 400 kHz

†

24LC515 2.5-5.5V 400 kHz I

24FC515 2.5-5.5V 1 MHz I

†

100 kHz for VCC < 2.5V.

VCC

SCL

SDA

PDIP

SOIJ

SCL

SDA

HV Generator

EEPROM

Array

Page Latches

YDEC

XDEC

Sense AMP

R/W

Control

Memory

Control

Logic

I/O

Control

Logic

I/O

A0A1

SDA

SCL

VSS

512K I

™

CMOS Serial EEPROM

*24XX515 is used in this document as a generic part number

for the 24AA515/24LC515/24FC515 devices.

Summary of content (24 pages)

PAGE 1
24AA515/24LC515/24FC515 512K I2C™ CMOS Serial EEPROM Device Selection Table Part Number VCC Range Max. Clock Frequency 24AA515 1.8-5.5V 400 kHz† I 24LC515 2.5-5.5V 400 kHz I 24FC515 2.5-5.5V 1 MHz I Temp. Ranges † 100 kHz for VCC < 2.5V. Reads may be sequential within address boundaries 0000h to 7FFFh and 8000h to FFFFh. Functional address lines allow up to four devices on the same data bus. This allows for up to 2 Mbits total system EEPROM memory.
PAGE 2
4AA515/24LC515/24FC515 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings(†) VCC .............................................................................................................................................................................6.5V All inputs and outputs w.r.t. VSS ......................................................................................................... -0.6V to VCC +1.0V Storage temperature ..................................................................
PAGE 3
24AA515/24LC515/24FC515 TABLE 1-2: AC CHARACTERISTICS AC CHARACTERISTICS Param. No. Sym. Industrial (I): Characteristic VCC = +1.7V to 5.5V TA = -40°C to +85°C Min. Max. Units Conditions 1 FCLK Clock frequency — — — 100 400 1000 kHz 1.7V ≤ VCC ≤ 2.5V 2.5V ≤ VCC ≤ 5.5V 2.5V ≤ VCC ≤ 5.5V (24FC515 only) 2 THIGH Clock high time 4000 600 500 — — — ns 1.7V ≤ VCC ≤ 2.5V 2.5V ≤ VCC ≤ 5.5V 2.5V ≤ VCC ≤ 5.5V (24FC515 only) 3 TLOW Clock low time 4700 1300 500 — — — ns 1.7V ≤ VCC ≤ 2.5V 2.
PAGE 4
24AA515/24LC515/24FC515 FIGURE 1-1: BUS TIMING DATA 5 SCL 7 SDA IN 3 4 D4 2 8 10 9 6 16 14 13 SDA OUT WP DS21673G-page 4 (protected) (unprotected) 11 12 © 2008 Microchip Technology Inc.
PAGE 5
24AA515/24LC515/24FC515 2.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 2-1. TABLE 2-1: Function A0 1 1 User Configurable Chip Select A1 2 2 User Configurable Chip Select A2 3 3 Non-Configurable Chip Select. This pin must be hard wired to logical 1 state (VCC). Device will not operate with this pin left floating or held to logical 0 (VSS). 4 4 Ground SDA 5 5 Serial Data SCL 6 6 Serial Clock WP 7 7 Write-Protect Input VCC 8 8 +1.7 to 5.5V (24AA515) +2.
PAGE 6
24AA515/24LC515/24FC515 4.0 BUS CHARACTERISTICS The data on the line must be changed during the low period of the clock signal. There is one bit of data per clock pulse. The following bus protocol has been defined: • Data transfer may be initiated only when the bus is not busy. • During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high will be interpreted as a Start or Stop condition.
PAGE 7
24AA515/24LC515/24FC515 5.0 DEVICE ADDRESSING FIGURE 5-1: A control byte is the first byte received following the Start condition from the master device (Figure 5-1). The control byte consists of a 4-bit control code; for the 24XX515, this is set as ‘1010’ binary for read and write operations. The next bit of the control byte is the block select bit (B0). This bit acts as the A15 address bit for accessing the entire array. The next two bits of the control byte are the Chip Select bits (A1, A0).
PAGE 8
24AA515/24LC515/24FC515 6.0 WRITE OPERATIONS 6.1 Byte Write Following the Start condition from the master, the control code (four bits), the block select (one bit) the Chip Select (two bits), and the R/W bit (which is a logic low) are clocked onto the bus by the master transmitter. This indicates to the addressed slave receiver that the address high byte will follow after it has generated an Acknowledge bit during the ninth clock cycle.
PAGE 9
24AA515/24LC515/24FC515 FIGURE 6-1: BYTE WRITE S T A R T Bus Activity Master Control Byte Address High Byte AA S1 01 0B 0 10 0 SDA Line Address Low Byte Data x P A C K Bus Activity S T O P A C K A C K A C K X = “don’t care” bit FIGURE 6-2: PAGE WRITE Bus Activity Master S T A R T SDA Line BAA S101 00 1 00 Control Byte Bus Activity Address High Byte Address Low Byte Data Byte 0 S T O P Data Byte 63 P x A C K A C K A C K A C K A C K X = “don’t care” bit © 2008 Microchip T
PAGE 10
24AA515/24LC515/24FC515 7.0 ACKNOWLEDGE POLLING Since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete. (This feature can be used to maximize bus throughput.) Once the Stop condition for a Write command has been issued from the master, the device initiates the internally timed write cycle. ACK polling can be initiated immediately. This involves the master sending a Start condition, followed by the control byte for a Write command (R/W = 0).
PAGE 11
24AA515/24LC515/24FC515 8.0 READ OPERATION 8.2 Read operations are initiated in the same way as write operations with the exception that the R/W bit of the control byte is set to one. There are three basic types of read operations: current address read, random read and sequential read. 8.1 Current Address Read The 24XX515 contains an address counter that maintains the address of the last word accessed, internally incremented by one.
PAGE 12
24AA515/24LC515/24FC515 FIGURE 8-2: Bus Activity Master SDA Line RANDOM READ S T A R T Control Byte Address High Byte S 1 0 1 0 B A A0 0 1 0 Control Byte S T O P Data Byte S 1 0 1 0 B A A1 0 1 0 x A C K A C K Bus Activity S T A R T Address Low Byte A C K P N O A C K A C K X = “don’t care” bit FIGURE 8-3: Bus Activity Master SEQUENTIAL READ Control Byte Data n Data n + 1 Data n + X Data n + 2 S T O P P SDA Line Bus Activity DS21673G-page 12 A C K A C K A C K A C K N O A C K
PAGE 13
24AA515/24LC515/24FC515 9.0 PACKAGING INFORMATION 9.1 Package Marking Information 8-Lead PDIP (300 mil) 24LC515 I/P e3 3L7 XXXXXXXX T/XXXNNN YYWW 0517 8-Lead SOIJ (5.28 mm) XXXXXXXX T/XXXXXX YYWWNNN Legend: XX...
PAGE 14
24AA515/24LC515/24FC515 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 N NOTE 1 E1 1 3 2 D E A2 A L A1 c e eB b1 b 6 &! ' ! 9 ' &! 7"') % ! 7,8. 7 7 & ; < & & 7: 1 , = = - 1 ! & & = = .
PAGE 15
24AA515/24LC515/24FC515 ! " " # $%& ! ' 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 D N E E1 1 2 e b α c φ A2 A β A1 6 &! ' ! 9 ' &! 7"') % ! L 99 . . 7 7 7: ; < & : 8 & = = < = : > #& . ? = < ? # # 4 > #& .
PAGE 16
24AA515/24LC515/24FC515 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS21673G-page 16 © 2008 Microchip Technology Inc.
PAGE 17
24AA515/24LC515/24FC515 APPENDIX A: REVISION HISTORY Revision C Corrections to Section 1.0, Electrical Characteristics. Revision D Removed Preliminary status. Revised conditions, Table 1-2, Param. 18. Revision E Revised Tables 1-1 and 2-1. Add Pb-free marking. Revision F Section 1.0 Electrical Characteristics: revised Ambient Temperature; Revised Section 2.1 and Section 2.5 Revision G (07/2008) Revised Features section; Revised 1.8V voltage to 1.
PAGE 19
24AA515/24LC515/24FC515 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
PAGE 20
24AA515/24LC515/24FC515 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document.
PAGE 21
24AA515/24LC515/24FC515 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X /XX Temperature Range Package Examples: a) b) Device: 24AA515: = 24AA515T: = 24LC515: = 24LC515T: = 24FC515: = 24FC515T: = 512K Bit 1.8V I2C CMOS Serial EEPROM 512K Bit 1.8V I2C CMOS Serial EEPROM (Tape and Reel) 512K Bit 2.5V I2C CMOS Serial EEPROM 512K Bit 2.5V I2C CMOS Serial EEPROM (Tape and Reel) 512K Bit 2.
PAGE 23
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PAGE 24
WORLDWIDE SALES AND SERVICE AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.