Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsIntegrated Circuits (ICs)SOIC 8 512 kBit 64 K x 8

24AA512/24LC512/24FC512

Device Selection Table

Features:

• Low-power CMOS technology:

- Maximum write current 5 mA at 5.5V

- Maximum read current 400 μA at 5.5V

- Standby current 100 nA typical at 5.5V

• 2-wire serial interface bus, I

™

compatible

• Cascadable for up to eight devices

• Self-timed erase/write cycle

• 128-byte Page Write mode available

• 5 ms max. write cycle time

• Hardware write-protect for entire array

• Schmitt Trigger inputs for noise suppression

• 1,000,000 erase/write cycles

• Electrostatic discharge protection > 4000V

• Data retention > 200 years

• 8-pin PDIP, SOIC (208 mil), and DFN packages

• 14-lead TSSOP package

• Standard and Pb-free finishes available

• Temperature ranges:

Description:

The Microchip Technology Inc. 24AA512/24LC512/

24FC512 (24XX512*) is a 64K x 8 (512 Kbit) Serial

Electrically Erasable PROM, capable of operation

across a broad voltage range (1.8V to 5.5V). It has

been developed for advanced, low-power applications

such as personal communications and data acquisi-

tion. This device also has a page write capability of up

to 128 bytes of data. This device is capable of both

random and sequential reads up to the 512K boundary.

Functional address lines allow up to eight devices on

the same bus, for up to 4 Mbit address space. This

device is available in the standard 8-pin plastic DIP,

SOIC, DFN and 14-lead TSSOP packages.

Block Diagram

Package Type

Part

Number

VCC

Range

Max. Clock

Frequency

Temp.

Ranges

24AA512 1.8-5.5V 400 kHz

(1)

24LC512 2.5-5.5V 400 kHz I, E

24FC512 2.5-5.5V 1 MHz I

Note 1: 100 kHz for V

CC < 2.5V

- Industrial (I): -40°C to +85°C

- Automotive (E): -40°C to +125°C

HV Generator

EEPROM

Array

Page Latches

YDEC

XDEC

Sense Amp.

R/W Control

Memory

Control

Logic

I/O

Control

Logic

I/O

A0 A1 A2

SDA

SCL

VSS

VCC

SCL

SDA

24XX512

PDIP SOIC

SCL

SDA

TSSOP

24XX512

DFN

SCL

SDA

24XX512

VCC

SCL

SDA

24XX512

512K I

™

CMOS Serial EEPROM

* 24XX512 is used in this document as a generic part number for the 24AA512/24LC512/24FC512 devices.

Summary of content (26 pages)

PAGE 1
24AA512/24LC512/24FC512 512K I2C™ CMOS Serial EEPROM Device Selection Table Description: Part Number VCC Range Max. Clock Frequency Temp. Ranges 24AA512 1.8-5.5V 400 kHz(1) I 24LC512 2.5-5.5V 400 kHz I, E 24FC512 2.5-5.5V 1 MHz I Note 1: The Microchip Technology Inc. 24AA512/24LC512/ 24FC512 (24XX512*) is a 64K x 8 (512 Kbit) Serial Electrically Erasable PROM, capable of operation across a broad voltage range (1.8V to 5.5V).
PAGE 2
4AA512/24LC512/24FC512 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (†) VCC .............................................................................................................................................................................6.5V All inputs and outputs w.r.t. VSS ......................................................................................................... -0.6V to VCC +1.0V Storage temperature .................................................................
PAGE 3
24AA512/24LC512/24FC512 TABLE 1-2: AC CHARACTERISTICS Electrical Characteristics: Industrial (I): VCC = +1.8V to 5.5V Automotive (E): VCC = +2.5V to 5.5V AC CHARACTERISTICS Param. No. Sym Characteristic Min Max Units TA = -40°C to +85°C TA = -40°C to +125°C Conditions 1 FCLK Clock frequency — — — 100 400 1000 kHz 1.8V ≤ VCC < 2.5V 2.5V ≤ VCC ≤ 5.5V 2.5V ≤ VCC ≤ 5.5V 24FC512 2 THIGH Clock high time 4000 600 500 — — — ns 1.8V ≤ VCC < 2.5V 2.5V ≤ VCC ≤ 5.5V 2.5V ≤ VCC ≤ 5.
PAGE 4
24AA512/24LC512/24FC512 FIGURE 1-1: BUS TIMING DATA 5 SCL SDA IN 7 3 4 D4 2 8 10 9 6 16 14 13 SDA OUT WP DS21754F-page 4 (protected) (unprotected) 11 12 © 2005 Microchip Technology Inc.
PAGE 5
24AA512/24LC512/24FC512 2.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 2-1. TABLE 2-1: 2.
PAGE 6
24AA512/24LC512/24FC512 4.0 BUS CHARACTERISTICS The following bus protocol has been defined: • Data transfer may be initiated only when the bus is not busy. • During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line, while the clock line is high, will be interpreted as a Start or Stop condition. Accordingly, the following bus conditions have been defined (Figure 4-1). 4.1 Bus Not Busy (A) Both data and clock lines remain high. 4.
PAGE 7
24AA512/24LC512/24FC512 FIGURE 4-1: (A) DATA TRANSFER SEQUENCE ON THE SERIAL BUS (B) (D) Start Condition Address or Acknowledge Valid (D) (C) (A) SCL SDA FIGURE 4-2: Data Allowed to Change Stop Condition ACKNOWLEDGE TIMING Acknowledge Bit SCL SDA 1 2 3 4 5 6 7 Data from transmitter Transmitter must release the SDA line at this point allowing the Receiver to pull the SDA line low to acknowledge the previous eight bits of data. © 2005 Microchip Technology Inc.
PAGE 8
24AA512/24LC512/24FC512 5.0 DEVICE ADDRESSING FIGURE 5-1: A control byte is the first byte received following the Start condition from the master device (Figure 5-1). The control byte consists of a 4-bit control code; for the 24XX512 this is set as ‘1010’ binary for read and write operations. The next three bits of the control byte are the Chip Select bits (A2, A1 and A0). The Chip Select bits allow the use of up to eight 24XX512 devices on the same bus and are used to select which device is accessed.
PAGE 9
24AA512/24LC512/24FC512 6.0 WRITE OPERATIONS 6.1 Byte Write Following the Start condition from the master, the control code (four bits), the Chip Select (three bits) and the R/W bit (which is a logic low) are clocked onto the bus by the master transmitter. This indicates to the addressed slave receiver that the address high byte will follow after it has generated an Acknowledge bit during the ninth clock cycle.
PAGE 10
24AA512/24LC512/24FC512 FIGURE 6-1: BYTE WRITE BUS ACTIVITY MASTER S T A R T CONTROL BYTE A C K A C K A C K PAGE WRITE BUS ACTIVITY MASTER S T A R T SDA LINE AAA S10 1 02 1 00 DS21754F-page 10 S T O P DATA P A C K BUS ACTIVITY BUS ACTIVITY ADDRESS LOW BYTE AA S1 01 0A 2 10 0 SDA LINE FIGURE 6-2: ADDRESS HIGH BYTE CONTROL BYTE ADDRESS HIGH BYTE ADDRESS LOW BYTE DATA BYTE 0 S T O P DATA BYTE 127 P A C K A C K A C K A C K A C K © 2005 Microchip Technology Inc.
PAGE 11
24AA512/24LC512/24FC512 7.0 ACKNOWLEDGE POLLING Since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). Once the Stop condition for a Write command has been issued from the master, the device initiates the internally timed write cycle. ACK polling can be initiated immediately. This involves the master sending a Start condition, followed by the control byte for a Write command (R/W = 0).
PAGE 12
24AA512/24LC512/24FC512 8.0 READ OPERATION 8.3 Read operations are initiated in the same way as write operations with the exception that the R/W bit of the control byte is set to ‘1’. There are three basic types of read operations: current address read, random read and sequential read. 8.1 Current Address Read The 24XX512 contains an address counter that maintains the address of the last word accessed, internally incremented by ‘1’.
PAGE 13
24AA512/24LC512/24FC512 FIGURE 8-2: BUS ACTIVITY MASTER SDA LINE RANDOM READ S T A R T CONTROL BYTE ADDRESS HIGH BYTE S T A R T ADDRESS LOW BYTE S1 01 0 AAA0 2 1 0 S T O P DATA BYTE S 1 0 1 0 A A A1 2 1 0 A C K BUS ACTIVITY CONTROL BYTE A C K A C K DATA (n + 1) DATA (n + 2) P N O A C K A C K X = “don’t care” bit FIGURE 8-3: BUS ACTIVITY MASTER SEQUENTIAL READ CONTROL BYTE DATA (n) S T O P DATA (n + X) P SDA LINE BUS ACTIVITY © 2005 Microchip Technology Inc.
PAGE 14
24AA512/24LC512/24FC512 9.0 PACKAGING INFORMATION 9.1 Package Marking Information 8-Lead PDIP (300 mil) 24AA512 I/P e3 017 0510 XXXXXXXX T/XXXNNN YYWW 8-Lead SOIC (208 mil) XXXXXXXX T/XXXXXX YYWWNNN 8-Lead DFN-S XXXXXXX T/XXXXX YYWW NNN 14-Lead TSSOP XXXXXXXT YYWW NNN Legend: XX...
PAGE 15
24AA512/24LC512/24FC512 8-Lead Plastic Dual In-line (P) – 300 mil (PDIP) E1 D 2 n 1 α E A2 A L c A1 β B1 p eB B Units Dimension Limits n p Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width Molded Package Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic A A2 A1 E E1 D L c
PAGE 16
24AA512/24LC512/24FC512 8-Lead Plastic Small Outline (SM) – Medium, 208 mil (SOIC) E E1 p D 2 1 n B α c A2 A φ L β Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Overall Length Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom A A2 A1 E E1 D L φ c B α β MIN .070 .069 .002 .300 .201 .202 .020 0 .008 .014 0 0 INCHES* NOM 8 .050 .075 .074 .005 .313 .208 .205 .025 4 .
PAGE 17
24AA512/24LC512/24FC512 8-Lead Plastic Dual Flat No Lead Package (MF) 6x5 mm Body (DFN-S) – Saw Singulated © 2005 Microchip Technology Inc.
PAGE 18
24AA512/24LC512/24FC512 14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP) E E1 p D 2 1 n B α A c φ β A1 L Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Molded Package Length Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic A A2 A1 E E1 D L φ c B α β MIN .033 .002 .246 .169 .193 .020 0 .004 .
PAGE 19
24AA512/24LC512/24FC512 APPENDIX A: REVISION HISTORY Revision D Correction to Section 1.0, Electrical Characteristics. Revision E Correction to Section 1.0., Ambient Temperature Correction to Section 6.2, Page Write Revision F Add E3 (Pb-free) to marking examples. Updated Marking Legend and On-line Support. © 2005 Microchip Technology Inc.
PAGE 21
24AA512/24LC512/24FC512 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
PAGE 22
24AA512/24LC512/24FC512 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document.
PAGE 23
24AA512/24LC512/24FC512 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X Device Device: Temperature Range 24AA512: 24AA512T: 24LC512: 24LC512T: 24FC512: 24FC512T: Temperature Range: I E Package: P = SM = ST14 = MF = Lead Finish = = /XX X Package Lead Finish 512 Kbit 1.8V I2C Serial EEPROM 512 Kbit 1.8V I2C Serial EEPROM (Tape and Reel) 512 Kbit 2.5V I2C Serial EEPROM 512 Kbit 2.
PAGE 25
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PAGE 26
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