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Table Of Contents
1998-2013 Microchip Technology Inc. DS20001203T-page 1
24AA256/24LC256/24FC256
Device Selection Table
Features:
• Single Supply with Operation Down to 1.7V for
24AA256 and 24FC256 Devices, 2.5V for
24LC256 Devices
• Low-Power CMOS Technology:
- Active current 400 uA, typical
- Standby current 100 nA, typical
• 2-Wire Serial Interface, I
2
C
™
Compatible
• Cascadable up to Eight Devices
• Schmitt Trigger Inputs for Noise Suppression
• Output Slope Control to Eliminate Ground Bounce
• 100 kHz and 400 kHz Clock Compatibility
• Page Write Time 5 ms Max.
• Self-Timed Erase/Write Cycle
• 64-Byte Page Write Buffer
• Hardware Write-Protect
• ESD Protection >4000V
• More than One Million Erase/Write Cycles
• Data Retention >200 years
• Factory Programming Available
• Packages Include 8-lead PDIP, SOIC, DFN,
TDFN, TSSOP and MSOP
• Pb-Free and RoHS Compliant
• Temperature Ranges:
Description:
The Microchip Technology Inc. 24AA256/24LC256/
24FC256 (24XX256*) is a 32K x 8 (256 Kbit) Serial
Electrically Erasable PROM, capable of operation
across a broad voltage range (1.7V to 5.5V). It has
been developed for advanced, low-power applications
such as personal communications or data acquisition.
This device also has a page write capability of up to 64
bytes of data. This device is capable of both random
and sequential reads up to the 256K boundary.
Functional address lines allow up to eight devices on
the same bus, for up to 2 Mbit address space. This
device is available in the standard 8-pin plastic DIP,
SOIC, TSSOP, MSOP, DFN and TDFN packages. The
24AA256 is also available in the 8-lead Chip Scale
package.
Block Diagram
Package Types
*24XX256 is used in this document as a generic part number for the 24AA256/24LC256/24FC256 devices.
Part
Number
VCC
Range
Max. Clock
Frequency
Temp.
Ranges
24AA256 1.7-5.5V 400 kHz
(1)
I, E
24LC256 2.5-5.5V 400 kHz I, E
24FC256 1.7-5.5V 1 MHz
(2)
I
Note 1: 100 kHz for V
CC < 2.5V.
2: 400 kHz for V
CC < 2.5V.
- Industrial (I): -40C to +85C
- Automotive (E): -40C to +125C
HV Generator
EEPROM
Array
Page Latches
YDEC
XDEC
Sense Amp.
R/W Control
Memory
Control
Logic
I/O
Control
Logic
I/O
A0 A1A2
SDA
SCL
V
CC
VSS
WP
A0
A1
A2
V
SS
VCC
WP
SCL
SDA
1
2
3
4
8
7
6
5
24XX256
PDIP/SOIC
TSSOP/MSOP
(1)
A0
A1
A2
V
SS
1
2
3
4
8
7
6
5
V
CC
WP
SCL
SDA
24XX256
DFN/TDFN
A0
A1
A2
V
SS
WP
SCL
SDA
24XX256
5
6
7
8
4
3
2
1
VCC
Note 1: * Pins A0 and A1 are no connects for the MSOP package only.
Note 2: Available in I-temp, “AA” only.
CS (Chip Scale)
(2)
12
3
45
6
7
8
V
CC A1 A0
WP A2
SDA SCL V
SS
(TOP DOWN VIEW,
BALLS NOT VISIBLE)
256K I
2
C™ CMOS Serial EEPROM

Summary of content (42 pages)