Data Sheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsIntegrated Circuits (ICs)EEPROM SOIC 8 256 kBit 32 K x 8

1998-2021 Microchip Technology Inc. DS20001203X-page 1

24AA256/24LC256/24FC256

Features

 Single Supply with Operation Down to 1.7V for

24AA256 and 24FC256 Devices, 2.5V for

24LC256 Devices

 Low-Power CMOS Technology:

- Write current: 3 mA, maximum

- Standby current: 1 μA maximum (I-temp.)

 Two-Wire Serial Interface, I

C Compatible

 Cascadable up to Eight Devices

 Schmitt Trigger Inputs for Noise Suppression

 Output Slope Control to Eliminate Ground Bounce

 100 kHz, 400 kHz and 1 MHz Compatibility

 Page Write Time: 5 ms, maximum

 Self-Timed Erase/Write Cycle

 64-Byte Page Write Buffer

 Hardware Write-Protect

 ESD Protection >4000V

 More than One Million Erase/Write Cycles

 Data Retention >200 years

 Factory Programming Available

 RoHS Compliant

 Temperature Ranges:

 Automotive AEC-Q100 Qualified

Packages

 8-Ball CSP, 8-Lead DFN, 8-Lead MSOP,

8-Lead PDIP, 8-Lead SOIC, 8-Lead SOIJ,

8-Lead TDFN and 8-Lead TSSOP

Description

The Microchip Technology Inc. 24XX256

(1)

is a 32K x 8

(256-Kbit) Serial Electrically Erasable PROM

(EEPROM), capable of operation across a broad volt-

age range (1.7V to 5.5V). It has been developed for

advanced, low-power applications such as personal

communications or data acquisition. This device also

has a page write capability of up to 64 bytes of data.

This device is capable of both random and sequential

reads up to the 256K boundary. Functional address

lines allow up to eight devices on the same bus, for up

to 2 Mbit address space.

Package Types

Device Selection Table

Part Number VCC Range

Maximum Clock

Frequency

Temperature

Ranges

Available Packages

24AA256 1.7V-5.5V 400 kHz

(1)

I, E CS, MF, MS, P, SN, SM, MNY, ST

24LC256 2.5V-5.5V 400 kHz I, E MF, MS, P, SN, SM, MNY, ST

24FC256 1.7V-5.5V 1 MHz

(2)

I MF, MS, P, SN, SM, MNY, ST

Note 1: 100 kHz for V

CC <2.5V.

2: 400 kHz for V

CC <2.5V.

- Industrial (I): -40 C to +85 C

- Extended (E): -40

C to +125 C

Note 1: 24XX256 is used in this document as a

generic part number for the

24AA256/24LC256/24FC256 devices.

CSP

123

CC A1 A0

WP A2

SDA SCL V

SOIC/SOIJ/TSSOP

DFN/TDFN

VSS

SCL

SDA

CC1

MSOP/PDIP

SCL

SDA

CC1

SCL

SDA

24XX256

Note 1: Pins A0 and A1 are no connects for the MSOP package only.

(1)

256-Kbit I

C Serial EEPROM

Summary of content (45 pages)

PAGE 1
24AA256/24LC256/24FC256 256-Kbit I2C Serial EEPROM Device Selection Table Part Number VCC Range Maximum Clock Frequency Temperature Ranges 1.7V-5.5V 400 kHz(1) I, E CS, MF, MS, P, SN, SM, MNY, ST 24AA256 Available Packages 24LC256 2.5V-5.5V 400 kHz I, E MF, MS, P, SN, SM, MNY, ST 24FC256 1.7V-5.5V 1 MHz(2) I MF, MS, P, SN, SM, MNY, ST Note 1: 2: 100 kHz for VCC < 2.5V. 400 kHz for VCC < 2.5V. Features Packages Single Supply with Operation Down to 1.
PAGE 2
4AA256/24LC256/24FC256 Block Diagram A0 A1A2 WP I/O Control Logic Memory Control Logic HV Generator XDEC EEPROM Array Page Latches I/O SCL YDEC SDA VCC VSS DS20001203X-page 2 Sense Amp. R/W Control 1998-2021 Microchip Technology Inc.
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24AA256/24LC256/24FC256 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings() VCC.............................................................................................................................................................................6.5V All inputs and outputs w.r.t. VSS ..........................................................................................................-0.6V to VCC +1.0V Storage temperature ...................................................................
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24AA256/24LC256/24FC256 TABLE 1-2: AC CHARACTERISTICS AC CHARACTERISTICS Param. Symbol No. 1 FCLK 2 THIGH 3 TLOW 4 TR 5 TF Characteristic Clock Frequency Clock High Time Clock Low Time SDA and SCL Rise Time SDA and SCL Fall Time THD:STA Start Condition Hold Time 6 7 TSU:STA Start Condition Setup Time 8 THD:DAT Data Input Hold Time TSU:DAT Data Input Setup Time 9 10 TSU:STO Stop Condition Setup Time Note 1: 2: 3: 4: Industrial (I): Extended (E): VCC = +1.7V to 5.5V VCC = +1.
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24AA256/24LC256/24FC256 TABLE 1-2: AC CHARACTERISTICS AC CHARACTERISTICS (Continued) Param. Symbol No.
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24AA256/24LC256/24FC256 FIGURE 1-1: BUS TIMING DATA 5 SCL 7 SDA IN 3 4 D3 2 8 10 9 6 16 14 13 SDA OUT WP DS20001203X-page 6 (protected) (unprotected) 11 12 1998-2021 Microchip Technology Inc.
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24AA256/24LC256/24FC256 2.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 2-1.
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24AA256/24LC256/24FC256 3.0 FUNCTIONAL DESCRIPTION The 24XX256 supports a bidirectional two-wire bus and data transmission protocol. A device that sends data onto the bus is defined as a transmitter and a device receiving data as a receiver. The bus must be controlled by a host device which generates the Serial Clock (SCL), controls the bus access, and generates the Start and Stop conditions while the 24XX256 works as a client.
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24AA256/24LC256/24FC256 FIGURE 4-1: (A) DATA TRANSFER SEQUENCE ON THE SERIAL BUS (B) (D) Start Condition Address or Acknowledge Valid (D) (C) (A) SCL SDA FIGURE 4-2: Data Allowed to Change Stop Condition ACKNOWLEDGE TIMING Acknowledge Bit SCL SDA 1 2 3 4 5 6 7 Data from transmitter Transmitter must release the SDA line at this point, allowing the Receiver to pull the SDA line low to acknowledge the previous eight bits of data. 1998-2021 Microchip Technology Inc.
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24AA256/24LC256/24FC256 5.0 DEVICE ADDRESSING FIGURE 5-1: A control byte is the first byte received following the Start condition from the host device. The control byte consists of a 4-bit control code. For the 24XX256, this is set as 1010 binary for read and write operations. The next three bits of the control byte are the Chip Select bits (A2, A1, A0). The Chip Select bits allow the use of up to eight 24XX256 devices on the same bus and are used to select which device is accessed.
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24AA256/24LC256/24FC256 6.0 WRITE OPERATIONS 6.1 Byte Write Following the Start condition from the host, the control code (four bits), the Chip Select (three bits) and the R/W bit (which is a logic low) are clocked onto the bus by the host transmitter. This indicates to the addressed client receiver that the address high byte will follow after it has generated an Acknowledge bit during the ninth clock cycle.
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24AA256/24LC256/24FC256 FIGURE 6-1: BYTE WRITE SDA Line S T A R T Bus Activity AA S1 0 1 0A 2 10 0 Bus Activity Host Control Byte Bus Activity Host SDA Line Bus Activity S T O P Data P A C K A C K A C K PAGE WRITE S T A R T Control Byte Address High Byte AAA S1010 2 1 0 0 x = dont care bit 7.
PAGE 13
24AA256/24LC256/24FC256 8.0 READ OPERATION 8.2 Random read operations allow the host to access any memory location in a random manner. To perform this type of read operation, the word address must first be set. This is done by sending the word address to the 24XX256 as part of a write operation (R/W bit set to 0). Once the word address is sent, the host generates a Start condition following the Acknowledge. This terminates the write operation, but not before the internal Address Pointer is set.
PAGE 14
24AA256/24LC256/24FC256 FIGURE 8-3: Bus Activity Host SEQUENTIAL READ Control Byte Data (n) Data (n + 1) S T O P Data (n + x) Data (n + 2) P SDA Line Bus Activity DS20001203X-page 14 A C K A C K A C K A C K N O A C K 1998-2021 Microchip Technology Inc.
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24AA256/24LC256/24FC256 9.0 PACKAGING INFORMATION 9.1 Package Marking Information 8-Lead Chip Scale Example XXX XYYW WNNN 249 A213 313F 8-Lead DFN-S Example XXXXXXX XXXXXXX YYWW NNN 24LC256 I/MF 2133 13F 8-Lead MSOP Example XXXXXX YWWNNN 4L256I 13313F 8-Lead PDIP (300 mil) Example XXXXXXXX XXXXXNNN YYWW 24AA256 I/P 13F 2133 8-Lead SOIC (3.90 mm) Example XXXXXXXX XXXXYYWW NNN 24LC256I SN 2133 13F 1998-2021 Microchip Technology Inc.
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24AA256/24LC256/24FC256 Package Marking Information (Continued) 8-Lead SOIJ (5.28 mm) Example XXXXXXXX XXXXXXXX YYWWNNN 24LC256 I/SM 213313F 8-Lead TDFN Example XXX YWW NN EF4 133 13 8-Lead TSSOP Example XXXX XYWW NNN Part No. 24AA256 4LD I133 13F 1st Line Marking Codes DFN MSOP PDIP SOIJ 4L256T(1) 24LC256 24FC256 24FC256 4F256T(1) TDFN TSSOP CSP 4AD 249 EF3 4LD 4FD I-Temp. E-Temp.
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24AA256/24LC256/24FC256 1998-2021 Microchip Technology Inc.
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24AA256/24LC256/24FC256 DS20001203X-page 18 1998-2021 Microchip Technology Inc.
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24AA256/24LC256/24FC256 1998-2021 Microchip Technology Inc.
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24AA256/24LC256/24FC256 DS20001203X-page 20 1998-2021 Microchip Technology Inc.
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24AA256/24LC256/24FC256 1998-2021 Microchip Technology Inc.
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24AA256/24LC256/24FC256 DS20001203X-page 22 1998-2021 Microchip Technology Inc.
PAGE 23
24AA256/24LC256/24FC256 # $ -) $2!- ) ) . !2 34-5 - . % ! / ) *0 1) *0 1 &)& % 4#- 34-5 -$# 34-5 ! 1998-2021 Microchip Technology Inc. " # $ %&'(&)*( + , - ) .
PAGE 24
AA256/24LC256/24FC256 /!-+$ !- /- # #- 4A$ B$2!- 8C # !6 # !6 1 1 . .
PAGE 25
24AA256/24LC256/24FC256 " # " $$ %& '( ')* ' "# + .0 & )& % D # # $2!- 8 $ . -) . -) - .0 & )& % D .0 & )& % . ) $2!- ) D $0 1 & .8 % D # $2!- 8 !2 34-5 & )& % % . - !4$A / $- *0 ) 4#- 34-5 & )& % +& )9 +& )9 7 & .
PAGE 26
24AA256/24LC256/24FC256 " # " $$ %& '( ')* ' "# + # $ 1 2, 7 ! ? 2, 5 5 2, / % B2 C / / ! / 5 # ! # $ 6 / $ . ) -) # / /) 1 4$ ( ) .
PAGE 27
24AA256/24LC256/24FC256 " # " $$ %& '( ')* ' "# + 4/G %+--$ % @) 0) - +-%2 -$#-# / $# !!-+$ # % % % % $ ) # 5 B0*C / B0*C 6 / % 0) @) 4$ 4//4 -!-+ $2 ) .
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24AA256/24LC256/24FC256 DS20001203X-page 28 1998-2021 Microchip Technology Inc.
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24AA256/24LC256/24FC256 1998-2021 Microchip Technology Inc.
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24AA256/24LC256/24FC256 DS20001203X-page 30 1998-2021 Microchip Technology Inc.
PAGE 31
24AA256/24LC256/24FC256 , & - . / 0 12 2 ' 3 , 4 5 )'62)' !27 8! !+ - . 7 4 , # $ B# !6 C B# !6 C $2!- ) .0 & )8 % ) . .0 & )8 % !2 34-5 & )& % B 9C % - !4$A / $- *0 ) & &* % 4#- 34-5 & )& % #. / ) . & )& % % % $2!- ) -.
PAGE 32
24AA256/24LC256/24FC256 , & - . / 0 12 2 ' 3 , 4 5 )'62)' !27 8! !+ - . 7 4 , # $ 1 2, 7 % ! 2, / 2, 5 -= / -= 5 % 5 % / % ( (-= 6 / $ ) 9 # #. -. 1 / G 4$ & <& & && ) 98 ) .8 & .& & .
PAGE 33
24AA256/24LC256/24FC256 , & - . / 0 12 2 ' 3 , 4 5 )'62)' !27 8! !+ - . 7 4 , 0. -3 * H3 % @. -3 @) ) . 4/G %+--$ 0) - +-%2 -$#-# / $# !!-+$ 6 / % 2 % 5 0. 2 % / @.
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24AA256/24LC256/24FC256 DS20001203X-page 34 1998-2021 Microchip Technology Inc.
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24AA256/24LC256/24FC256 1998-2021 Microchip Technology Inc.
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24AA256/24LC256/24FC256 DS20001203X-page 36 1998-2021 Microchip Technology Inc.
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24AA256/24LC256/24FC256 1998-2021 Microchip Technology Inc.
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24AA256/24LC256/24FC256 DS20001203X-page 38 1998-2021 Microchip Technology Inc.
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24AA256/24LC256/24FC256 1998-2021 Microchip Technology Inc.
PAGE 40
24AA256/24LC256/24FC256 APPENDIX A: REVISION HISTORY Revision X (10/2021) Replaced terminology Master and Slave with Host and Client respectively; Added Automotive Product Identification System; Updated DFN, PDIP, SOIC, TDFN and TSSOP package drawings. Revision W (08/2019) Updated content throughout for clarification. Revision V (08/2018) Updated First Line Marking Codes table. Revision U (11/2013) Updated ICCS. Revision T (04/2013) Added TDFN Package.
PAGE 41
24AA256/24LC256/24FC256 THE MICROCHIP WEBSITE CUSTOMER SUPPORT Microchip provides online support via our website at www.microchip.com. This website is used as a means to make files and information easily available to customers.
PAGE 42
24AA256/24LC256/24FC256 PRODUCT IDENTIFICATION SYSTEM (NON-AUTOMOTIVE) To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. [X] PART NO. Device (1) Tape and Reel Option -X /XX Temperature Range Package Device: 24AA256 = 1.7V, 256-Kbit I2C Serial EEPROM 24LC256 = 2.5V, 256-Kbit I2C Serial EEPROM 24FC256 = 1.
PAGE 43
24AA256/24LC256/24FC256 PRODUCT IDENTIFICATION SYSTEM (AUTOMOTIVE) To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. (1) PART NO. Device Device: Tape and Reel Option 24LC256 = 24FC256 = (2, 3) X /XX XXX Temperature Range Package Variant [X] 2.5V, 256-Kbit I2C Serial EEPROM 1.
PAGE 44
Note the following details of the code protection feature on Microchip products: Microchip products meet the specifications contained in their particular Microchip Data Sheet. Microchip believes that its family of products is secure when used in the intended manner, within operating specifications, and under normal conditions. Microchip values and aggressively protects its intellectual property rights.
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