Datasheet

24LC21
DS21095K-page 6  1994-2012 Microchip Technology Inc.
3.1.4 DATA VALID (D)
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of the
data bytes transferred between the Start and Stop
conditions is determined by the master device and is
theoretically unlimited, although only the last eight will
be stored when doing a write operation. When an
overwrite does occur, it will replace data in a first in first
out fashion.
3.1.5 ACKNOWLEDGE
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this Acknowledge bit.
The device that acknowledges has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable low during the high
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an Acknowledge bit on the last
byte that has been clocked out of the slave. In this
case, the slave must leave the data line high to enable
the master to generate the Stop condition.
FIGURE 3-3: BUS TIMING START/STOP
FIGURE 3-4: BUS TIMING DATA
Note: The 24LC21 does not generate any
Acknowledge bits if an internal program-
ming cycle is in progress.
TSU:STA
THD:STA
VHYS
TSU:STO
Start Stop
SCL
SDA
TSU:STA
TF
TLOW
THIGH
TR
THD:DAT TSU:DAT TSU:STO
THD:STA
TBUF
TAA
TAA
TSP
THD:STA
SCL
SDA
IN
SDA
OUT
21095K.book Page 6 Wednesday, December 5, 2012 2:28 PM