Datasheet

24LC21
DS21095K-page 4  1994-2012 Microchip Technology Inc.
2.0 FUNCTIONAL DESCRIPTION
The 24LC21 operates in two modes, the Transmit-only
mode and the Bidirectional mode. There is a separate
two-wire protocol to support each mode, each having a
separate clock input and sharing a common data line
(SDA). The device enters the Transmit-only mode upon
power-up. In this mode, the device transmits data bits
on the SDA pin in response to a clock signal on the
V
CLK pin. The device will remain in this mode until a
valid high-to-low transition is placed on the SCL input.
When a valid transition on SCL is recognized, the
device will switch into the Bidirectional mode. The only
way to switch the device back to the Transmit-only
mode is to remove power from the device.
2.1 Transmit-only Mode
The device will power-up in the Transmit-only mode.
This mode supports a unidirectional two-wire protocol
for transmission of the contents of the memory array.
This device requires that it be initialized prior to valid
data being sent in the Transmit-only mode (see Initial-
ization Procedure, below). In this mode, data is trans-
mitted on the SDA pin in 8-bit bytes, each followed by
a ninth, null bit (see Figure 2-1). The clock source for
the Transmit-only mode is provided on the V
CLK pin,
and a data bit is output on the rising edge on this pin.
The eight bits in each byte are transmitted Most Signif-
icant bit first. Each byte within the memory array will be
output in sequence. When the last byte in the memory
array is transmitted, the output will wrap around to the
first location and continue. The Bidirectional mode
Clock (SCL) pin must be held high for the device to
remain in the Transmit-only mode.
2.2 Initialization Procedure
After VCC has stabilized, the device will be in the Trans-
mit-only mode. Nine clock cycles on the V
CLK pin must
be given to the device for it to perform internal synchro-
nization. During this period, the SDA pin will be in a
high-impedance state. On the rising edge of the tenth
clock cycle, the device will output the first valid data bit
which will be the Most Significant bit of a byte. The
device will power-up at an indeterminate byte address.
(Figure 2-2).
FIGURE 2-1: TRANSMIT-ONLY MODE
FIGURE 2-2: DEVICE INITIALIZATION
SCL
SDA
V
CLK
TVAA TVAA
Bit 1 (LSB)
Null Bit
Bit 1 (MSB) Bit 7
T
VLOWTVHIGH
TVAA TVAA
Bit 8 Bit 7High-impedance for 9 clock cycles
TVPU
12 891011
SCL
SDA
V
CLK
VCC
21095K.book Page 4 Wednesday, December 5, 2012 2:28 PM